Write Back Monitor Circuit for Multiprocessor Cache Coherence

The patent extracts the cache coherence management function from the hardware circuit domain and relocates it to the software domain. Instead of using a dedicated cache coherence circuit to automatically track and invalidate cache copies, the system uses a write back monitor circuit to buffer write addresses and relies on compiler-generated commands in the program to explicitly manage cache invalidation. This extraction of the coherence management function from hardware to software dramatically reduces circuit complexity while maintaining coherence reliability.

The patent implements a self-service mechanism where the program itself is responsible for managing its own cache coherence. The write back monitor circuit provides a service by buffering write addresses and making them available to the program via read commands, but the actual coherence enforcement is performed by the program executing coherence management instructions generated by the compiler. This self-service approach eliminates the need for complex real-time hardware arbitration and tracking circuits, thereby reducing processing delays while maintaining data consistency.

The patent makes the processor instruction cycles multi-functional by using them for both regular program execution and cache coherence management. The compiler generates regular program instructions that also serve as coherence management commands when executed. The write back monitor circuit buffers write addresses and makes them available during normal instruction execution flow, allowing coherence management to be integrated into the regular instruction cycle rather than requiring separate dedicated coherence management cycles. This universality allows the same instruction cycles to accomplish both computation and coherence enforcement.