Write Booster Disablement for Saturated Flash Memory

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Solution Overview

Problem

Memory systems face reduced storage capacity and performance inefficiencies during high levels of logical saturation due to the inability to dynamically manage write booster modes, leading to unused SLC blocks and increased response times.

Innovation Solution

The system dynamically disables the write booster mode and reallocates SLC blocks for non-write-booster operations when saturation exceeds a threshold, re-enabling it when saturation decreases, thereby optimizing storage capacity and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If write booster mode is enabled to improve write performance, then write speed is improved, but storage capacity is reduced due to unused SLC blocks during high logical saturation

Engineering Contradiction:
Improvewrite speedVSAvoidstorage capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent implements dynamic switching between write booster mode and normal mode based on real-time logical saturation levels. When saturation exceeds a threshold, the system transitions from write booster mode (which reserves SLC blocks for fast writing) to normal mode (which utilizes all available TLC blocks), thereby adapting storage capacity and performance characteristics to current system conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (write booster enable/disable state) based on the logical saturation parameter. By monitoring saturation levels and adjusting the write mode accordingly, the system optimizes the trade-off between write performance and available storage capacity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If write booster mode is continuously enabled to maintain performance, then write performance is preserved, but system responsiveness deteriorates during high saturation due to inability to reallocate blocks

Engineering Contradiction:
Improvewrite performanceVSAvoidresponse time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system continuously monitors logical saturation levels and uses this feedback to dynamically adjust write booster mode status. This closed-loop control ensures that the system responds to changing conditions in real-time, disabling write booster when saturation is high to improve responsiveness and re-enabling it when saturation decreases to restore performance optimization.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The write mode transitions from static to dynamic, allowing the system to adapt its performance characteristics based on operational conditions. This dynamic adjustment eliminates the fixed trade-off between performance and responsiveness by allowing real-time optimization.

Inventive Principle:
Principle #15Dynamics

3Speed

If SLC blocks are reserved for write booster operations, then write performance is improved, but storage efficiency decreases during high logical saturation

Engineering Contradiction:
Improvewrite performanceVSAvoidstorage efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The SLC blocks serve dual purposes: they function as write booster cache when logical saturation is low (improving write performance), and as additional storage capacity when logical saturation is high (improving storage efficiency). This multi-functionality resolves the contradiction by allowing the same hardware resources to serve different functions based on system needs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250355583A1Dynamic write booster disablement
Publication Date: 2025.11.20 MICRON TECHNOLOGY INC
  • US20250355583A1 patent drawing
  • US20250355583A1 patent drawing
  • US20250355583A1 patent drawing

AI summary

Methods, systems, and devices for dynamic write booster disablement are described. A memory system may determine whether a quantity of data stored to the memory system satisfies a first threshold value. In some examples, a block of memory cells of the memory system may be allocated to a write booster cursor. The memory system may disable operation of a write booster mode in response to determining that the quantity of data satisfies the first threshold value. As such, the memory system may allocate the block of memory cells of the write booster cursor to store data in response to disabling the operation of the write booster mode. If the quantity of data satisfies a second threshold value, the memory system may determine to open a second write booster cursor and allocate a second block of memory cells to the second write booster cursor.