Write Booster SLC Pinning for Lower Memory Access Latency
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Solution Overview
Problem
Existing memory devices face performance issues due to the increased latency caused by moving data from single-level cells (SLCs) to multi-level cells (MLCs) during operations, which affects overall throughput and access speed.
Innovation Solution
Implementing a write booster mode that pins frequently accessed data to single-level cells (SLCs) and unpins less-frequently accessed data to multi-level cells (MLCs), optimizing the use of SLCs for improved performance and availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is moved from SLCs to MLCs during operations, then storage capacity is improved, but access latency increases
Solution Approach 1:
The memory array is segmented into two distinct portions: a first portion comprising SLCs for high-speed access and a second portion comprising MLCs for capacity storage. This segmentation allows the system to simultaneously achieve both low latency for frequently accessed data and high capacity for overall storage, resolving the contradiction between storage capacity and access latency.
2Speed
If SLCs are used for frequent access, then access speed is improved, but the number of available SLCs decreases
Solution Approach 1:
The system dynamically manages the allocation of SLCs through pinning and unpinning operations. Frequently accessed data is pinned to SLCs to maintain high access speed, while less frequently accessed data is unpinned and moved to MLCs to free up SLCs for future high-speed access needs. This dynamic management resolves the contradiction between maintaining access speed and having available SLCs.
3Loss of time
If data is pinned to SLCs, then access latency is reduced, but device complexity increases
Solution Approach 1:
The system implements a feedback mechanism where the controller monitors access patterns and dynamically adjusts data placement between SLCs and MLCs based on actual usage. This feedback-driven approach reduces access latency for frequently accessed data while managing complexity through automated decision-making rather than manual configuration.
Data Source
AI summary
Methods, systems, and devices for write booster pinning are described. In some examples, a memory device may receive one or more commands (e.g., write commands) while operating in a first mode (e.g., a write booster mode). Some write commands may include an indication to pin the data to one or more SLCs. For example, a first write command may be associated with first data and a first indicator and a second write command may be associated with second data. Both the first data and the second data may be written to one or more SLCs. When maintenance operations are performed on the SLCs, the second data may be moved (e.g., written) to one or more MLCs. Additionally or alternatively, the memory system may receive one or more commands to unpin data (e.g., the first data) such that it may be moved to one or more MLCs during subsequent maintenance operations.