Write Buffer Logic for Multicore Cache Coherency Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multicore systems, the frequent generation of snoops due to cache coherency issues leads to performance deterioration, as access from CPU cores to cache memory is often delayed, especially when many snoops are generated.
Innovation Solution
The implementation of a write buffer with multiple stages, where data to be written to external memory is stored along with its address, and a control part that compares the write destination address with stored addresses, logically moving matching data to the last stage, thereby reducing snoop requests and improving cache access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a snoop function is implemented in cache memory to maintain cache coherency among CPUs, then cache coherency is maintained, but access from CPU core to cache memory is delayed due to exclusive access requirements, leading to performance deterioration
Solution Approach 1:
The patent introduces a write buffer as an intermediary component between the cache memory and external memory. This buffer absorbs write operations and manages data transfer asynchronously, allowing CPU accesses to proceed without being blocked by snoop operations. The write buffer acts as a mediator that decouples the exclusive access requirements of the cache memory from the continuous data flow needs of the CPU, thereby maintaining cache coherency while improving access speed.
2Reliability
If multiple snoops are generated to maintain cache coherency, then cache coherency is ensured, but CPU core access to cache memory is frequently delayed, leading to performance deterioration
Solution Approach 1:
The patent implements preliminary action by pre-loading data into the write buffer before actual write operations to external memory are completed. The write buffer pre-manages data staging and address buffering, so when snoop operations occur, the data is already prepared and can be accessed or invalidated without causing CPU access delays. This preliminary preparation reduces the time loss associated with frequent snoop operations.
3Productivity
If a write buffer is provided between cache memory and external memory to absorb write time, then write throughput is improved, but cache coherency management becomes more complex
Solution Approach 1:
The write buffer is designed with self-service capabilities including automatic address comparison, buffer stage management, and coherence state tracking. The control part within the write buffer autonomously manages data staging, address matching, and coordination with cache memory without requiring complex external control logic. This self-managing approach improves write throughput while keeping the cache coherency management architecture relatively simple.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
In a multicore system in which a plurality of CPUs each including a cache memory share one main memory, a write buffer having a plurality of stages of buffers each holding data to be written to the main memory and an address of a write destination is provided between the cache memory and the main memory, and at the time of a write to the write buffer from the cache memory, an address of a write destination and the addresses stored in the buffers are compared, and when any of the buffers has an agreeing address, data is overwritten to this buffer, and the buffer is logically moved to a last stage.