Memory Write Buffer Checksum Reflection for High-Speed Error Coverage
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Solution Overview
Problem
As interconnect signaling speeds increase, the bit error rate (BER) in memory systems, such as DRAM, also rises, and existing error detection techniques like CRC struggle to provide adequate error coverage without significant logic overhead in memory devices.
Innovation Solution
The memory device reflects back error detection signals, such as CRC checksums, to the memory controller for comparison, eliminating the need for local calculation and enhancing error coverage with rolling checksums across multiple frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stronger CRC codes are used to improve error coverage, then error detection capability is improved, but device complexity increases due to significant logic overhead in the memory device
Solution Approach 1:
The patent extracts the CRC calculation function from the memory device and relocates it to the memory controller. The memory device only needs to store the checksum and reflect it back, while the memory controller performs the computationally intensive CRC calculation and comparison. This extraction eliminates the logic overhead in the memory device while maintaining error detection capability.
Solution Approach 2:
The patent introduces a checksum as an intermediary element that carries error detection information between the memory controller and memory device. The checksum is calculated by the controller, stored by the device, and reflected back for verification. This intermediary mechanism enables error detection without requiring complex logic in the memory device.
2Productivity
If interconnect signaling speed is increased to improve productivity, then data transmission speed is improved, but the bit error rate increases
Solution Approach 1:
The patent implements a feedback mechanism where the memory device reflects the stored checksum back to the memory controller. The controller compares the reflected checksum with a newly calculated checksum to detect errors. This feedback loop enables error detection at high signaling speeds by providing a verification mechanism that operates independently of transmission speed.
Solution Approach 2:
The patent performs preliminary CRC calculation and checksum generation at the memory controller before data is written to the memory device. This preliminary action prepares the error detection information in advance, allowing the memory device to simply store and reflect it back without performing complex calculations during high-speed write operations.
Data Source
AI summary
In some embodiments, a chip includes a memory core, a write buffer, transmitters, receivers to receive groups of signals including write data signals and associated error detection signals, and circuitry to provide the error detection signals to the transmitters to be transmitted to another chip and to provide the write data signals to the write buffer. The write data signals are held in the write buffer at least until it is determined whether their associated transmitted error detection signals match corresponding error detection signals stored in the other chip. Other embodiments are described and claimed.