Write Buffer Flush Scheme for High Density Memory

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Solution Overview

Problem

Existing memory systems with multi-level cell (MLC) or triple-level cell (TLC) memory architectures face throughput degradation due to fragmented data in the write buffer, leading to non-contiguous available memory space.

Innovation Solution

A memory controller maintains a list of data segments in the write buffer, sorted by available contiguous memory space, and initiates flush operations based on this list to optimize memory space utilization and prevent direct writing to main storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is written to random locations in the write buffer to speed up write operations, then write speed is improved, but data fragmentation increases and available memory space becomes non-contiguous

Engineering Contradiction:
Improvewrite speedVSAvoiddata contiguity
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The write buffer is divided into multiple blocks, and the patent implements a block-based flush strategy where complete blocks are flushed together. This segmentation allows the system to maintain contiguity at the block level while still enabling fast random write operations at the cell level, resolving the contradiction between write speed and data contiguity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-flushing complete blocks from the write buffer before they become fragmented. By monitoring block fill status and proactively flushing complete blocks, the system prevents fragmentation from developing and maintains contiguous available space, thus preserving both write speed and data organization.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the write buffer becomes fragmented with non-contiguous available space, then write operations can still be performed, but throughput degrades when incoming data exceeds available contiguous space

Engineering Contradiction:
Improvememory system throughputVSAvoidmemory space management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a dynamic flush strategy where the decision to flush a block depends on real-time conditions such as block fill status, available contiguous space, and incoming data size. This dynamic approach allows the system to adapt to changing memory states and maintain optimal throughput without requiring complex static management rules.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes key parameters including block size, flush threshold, and available contiguous space monitoring to optimize throughput. By adjusting these parameters dynamically based on workload characteristics, the system maintains high productivity while managing memory space complexity through simplified parameter-based decision making.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If a simple flush strategy is used without tracking available contiguous space, then device complexity is reduced, but write buffer space utilization becomes inefficient

Engineering Contradiction:
Improveflush control complexityVSAvoidwrite buffer space utilization
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent introduces an intermediary data structure (the block status table) that tracks the fill status of each block in the write buffer. This intermediary structure enables efficient space utilization by providing precise information about available contiguous space without requiring complex global tracking mechanisms, thus balancing simplicity with effectiveness.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent ensures equipotentiality by treating all blocks in the write buffer equally for flushing purposes, regardless of their specific location or data content. The uniform block-based approach simplifies control logic while maximizing space utilization through consistent treatment of all buffer regions, avoiding preferential treatment that would complicate the management system.

Inventive Principle:
Principle #12Equipotentiality

Data Source

PatentUS20250156334A1Enhanced write buffer flush scheme for memory devices with high density storage memory architecture
Publication Date: 2025.05.15 QUALCOMM INC
  • US20250156334A1 patent drawing
  • US20250156334A1 patent drawing
  • US20250156334A1 patent drawing

AI summary

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.