Write Buffer L2P Extension for Lower Memory Mapping Latency

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Solution Overview

Problem

Memory systems face inefficiencies in managing logical-to-physical (L2P) table storage, leading to increased latency and resource wastage due to the allocation of volatile memory for L2P tables, especially when handling random read requests and small chunk write requests.

Innovation Solution

Implementing a configurable L2P table storage extension that shares a write buffer for both host write data and L2P tables, with defined ranges for buffer unit allocation, allowing partial or full L2P extension to optimize memory usage and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If volatile memory is allocated for L2P tables, then L2P table storage capacity is improved, but memory resource utilization deteriorates

Engineering Contradiction:
ImproveL2P table storage capacityVSAvoidmemory resource utilization
Core Design Contradiction:
Quantity of substanceVSLoss of energy

Solution Approach 1:

The patent merges the L2P table storage function with the existing write buffer resource. Instead of allocating separate volatile memory for L2P tables, the system combines L2P table storage with the write buffer, allowing the same memory resource to serve dual purposes: buffering write data and storing L2P table mappings.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The write buffer is designed to perform multiple functions: it serves as both a write data buffer and an L2P table storage area. This multi-functionality eliminates the need for dedicated volatile memory allocation for L2P tables, improving overall memory resource utilization while maintaining sufficient L2P table storage capacity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If volatile memory is allocated for L2P tables, then L2P table access speed is improved, but system latency deteriorates

Engineering Contradiction:
ImproveL2P table access speedVSAvoidsystem latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The system performs preliminary actions by pre-loading L2P table data into the write buffer before it is needed for random read operations. This advance preparation ensures that L2P tables are already in memory when required, eliminating access delays and reducing system latency for random read requests.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuous utilization of the write buffer for both write data buffering and L2P table storage. By keeping the buffer continuously occupied with useful data (either write data or L2P tables), the system avoids idle memory access operations and maintains high-speed access without incurring additional latency.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If write buffer is dedicated for host write data, then write data handling is improved, but L2P table storage deteriorates

Engineering Contradiction:
Improvewrite data handlingVSAvoidL2P table storage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic allocation within the write buffer, where the buffer can adaptively switch between storing write data and storing L2P tables based on system needs. This dynamic usage allows the same physical buffer to support both write data handling and L2P table storage without requiring dedicated resources for each function.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the functional parameter of the write buffer from a fixed write-data-only role to a flexible role that can store either write data or L2P tables. This parameter change enables the buffer to expand its functionality to include L2P table storage while maintaining its original write data handling capabilities.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250383800A1Configurable logical-to-physical table storage extension at a memory system
Publication Date: 2025.12.18 MICRON TECHNOLOGY INC
  • US20250383800A1 patent drawing
  • US20250383800A1 patent drawing
  • US20250383800A1 patent drawing

AI summary

Methods, systems, and devices for configurable logical-to-physical table storage extension at a memory system are described. The described techniques provide for a memory system to share host write data and logical-to-physical (L2P) extension data within a write buffer. If the memory system triggers L2P extension, the memory system may compare a quantity of available buffer units with an upper bound of a range of buffer units configured for L2P extension. For example, if enough buffer units are available for a full L2P extension, the memory system may allocate a full L2P extension, and if there are not enough buffer units available, the memory system may allocate a partial L2P extension. If the memory system allocates a partial L2P extension, the memory system may begin flushing write data stored to the buffer and may allocate newly available buffer units for the L2P extension.