Write Buffer Coherency for Low-Latency SoC Memory Traffic
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Solution Overview
Problem
Existing SoC architectures face inefficiencies in data traffic management between processors and DMA channels due to high latency and data coherency issues, exacerbated by the use of multiple cache levels which increase die size and manufacturing costs.
Innovation Solution
A system with a write buffer unit and snooper logic is introduced to minimize write requests to primary storage, ensuring data consistency and reducing the need for multiple cache levels by using a write buffer to temporarily store data and manage coherency between processors and DMA channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple cache levels (L1, L2, L3) are used to reduce access latency, then data access speed is improved, but die size increases due to larger SRAM blocks
Solution Approach 1:
The patent extracts the write buffering function from the traditional multi-level cache hierarchy and implements it as a separate write buffer unit in the external memory interface. This removes the need for multiple cache levels while maintaining data access efficiency, as the write buffer handles write operations independently without requiring large L2/L3 cache structures.
Solution Approach 2:
The write buffer unit acts as an intermediary between the processor and main memory, temporarily storing write data and managing write operations. This intermediary structure eliminates the need for multiple cache levels by providing a dedicated buffer that handles write traffic efficiently, reducing die size while maintaining performance.
2Productivity
If multiple cache levels are implemented to improve data locality, then data access efficiency is improved, but manufacturing cost increases due to larger die size
Solution Approach 1:
The patent extracts the write buffering functionality from the complex multi-level cache structure and places it in the external memory interface as a separate write buffer unit. This simplification reduces die size and manufacturing cost while preserving data access efficiency through targeted write optimization.
Solution Approach 2:
The patent changes the architectural parameter from multiple cache levels to a single write buffer unit in the external memory interface. This parameter change maintains data access efficiency by optimizing write operations specifically, while reducing the overall SRAM requirement and manufacturing cost.
3Loss of time
If write buffer unit is used to minimize write requests, then latency is reduced and write traffic efficiency is improved, but data coherency management complexity increases
Solution Approach 1:
The write buffer unit serves as an intermediary that simplifies coherency management by centralizing write operation handling in the external memory interface. The snooper logic within the write buffer monitors and manages data coherency between processor and DMA channels, reducing latency while keeping coherency management organized and localized rather than distributed across multiple cache levels.
Solution Approach 2:
The write buffer unit performs multiple functions including temporary write data storage, write request minimization through coalescing, and data coherency management via snooper logic. This multi-functional design reduces overall system complexity by consolidating these functions in a single unit rather than requiring separate mechanisms for each function.
4Productivity
If write buffer unit consolidates write requests, then the number of write requests to main memory is reduced, but the buffer unit requires additional SRAM resources
Solution Approach 1:
The write buffer unit acts as an intermediary between processor and main memory, using a relatively small SRAM buffer to consolidate write requests. This intermediary approach requires minimal SRAM resources compared to full multi-level caches, while achieving significant write traffic efficiency through write coalescing and batching operations.
Solution Approach 2:
Instead of implementing full multi-level caches with extensive SRAM resources, the patent applies partial action by implementing only the essential write buffering function in the external memory interface. This partial implementation achieves the critical goal of reducing write requests to main memory while using minimal SRAM resources, avoiding the excessive resource consumption of complete cache hierarchies.
Data Source
AI summary
The present invention relates to a system (101) and method for primary storage write traffic management, which can improve the overall system on chip (SoC) data traffic efficiency between the processor (103), direct memory access (DMA) channel (111) and the main memory (113), by minimizing the latency to write the data to the main memory (113). This is done by reducing the number of writes from the processor (103) to the main memory (113) without sacrificing data consistency between the processor (103) and the DMA channel (111).