Write Buffer Design for High-Latency NVM
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Solution Overview
Problem
Non-volatile memory (NVM) technologies, such as flash memory, experience high write latency and wear-out due to frequent writes, impacting performance and longevity in computing systems.
Innovation Solution
A write buffering scheme utilizing a hash table and linked list is implemented to buffer write accesses, providing cache-like behavior without the need for a separate cache tag array, and can be implemented in hardware, software, or firmware, using a fast low-latency memory like DRAM to manage write requests and reduce contention in main NVM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write accesses are buffered using a hash table and linked list structure, then write performance and NVM lifespan are improved, but memory controller complexity increases
Solution Approach 1:
The write buffer is segmented into multiple sets, with each set containing multiple ways (entry points). This segmentation allows parallel access to different portions of the buffer, improving write performance while distributing the complexity across multiple simpler components rather than one complex monolithic structure.
Solution Approach 2:
The patent introduces a multi-dimensional buffer structure with sets and ways, adding spatial organization to the buffering mechanism. This dimensional approach allows efficient hashing and collision handling by distributing writes across multiple dimensions (set index, way index, entry offset), resolving complexity through structured organization.
2Productivity
If a multi-set multi-way write buffer structure is used, then write throughput and bandwidth utilization are improved, but buffer management complexity increases
Solution Approach 1:
The buffer pre-allocates entries and maintains ready-state buffers before they are needed. Write requests are prepared and staged in the buffer structure in advance, allowing the system to handle writes more efficiently when bandwidth becomes available, rather than reacting to each write request individually.
Solution Approach 2:
The write buffer acts as an intermediary between the host processor and the NVM, absorbing write requests and managing them according to available bandwidth. This intermediary structure decouples the high-speed write requests from the slower NVM write operations, improving throughput while managing complexity through the buffer's mediation layer.
3Reliability
If write requests are held in buffer until bandwidth is available, then NVM wear-out is reduced, but buffer occupancy and potential data loss risk increase
Solution Approach 1:
The buffer implements a policy of discarding writes that cannot be flushed within a certain time or when the buffer is full, while recovering and retrying them later when bandwidth becomes available. This approach prevents buffer overflow and data loss while still protecting NVM from excessive wear by avoiding immediate writes.
Solution Approach 2:
The system periodically flushes the write buffer to NVM when bandwidth becomes available, rather than writing immediately or holding indefinitely. This periodic action balances buffer occupancy by emptying the buffer at regular intervals, reducing the risk of data loss while still reducing NVM wear by batching writes.
Data Source
AI summary
A memory system includes a write buffer, a main memory having a higher latency than the write buffer, and a memory controller. In response to a write request indicating first data for storing at a write address in the main memory, the memory controller adds a new write entry in the write buffer, where the new write entry includes the write address and the first data, and updates a pointer of a previous write entry in the write buffer to point to the new write entry. In response to a write-back instruction, the memory controller traverses a plurality of write entries stored in the write buffer, and writes into the main memory second data of the previous write entry and the first data of the new write entry.