Write Combining Buffer for Ordered Store Release Processing
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Solution Overview
Problem
The use of store release instructions in processor pipelines leads to reduced throughput performance due to the need to wait for all pending, older store instructions to be committed before processing can continue, causing pipeline bubbles and inefficiencies, especially when a large number of such instructions are used.
Innovation Solution
A write buffer circuit is configured to allow store release instructions to be launched into a combining buffer even if there are pending, older store instructions not yet committed, delaying the release of these instructions until all pending store instructions have been committed, thereby avoiding pipeline bubbles and enabling combining of multiple store release instructions for efficient processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If store release instructions wait for all pending older store instructions to be committed before processing, then memory ordering correctness is ensured, but processor throughput performance deteriorates due to pipeline bubbles
Solution Approach 1:
The write buffer circuit launches store release instructions into the combining buffer in advance, before all pending older store instructions have been committed. This preliminary action allows the instruction pipeline to continue processing without bubbles, while the actual memory write operation is delayed until ordering requirements are satisfied. The combining buffer holds the instruction until it can be safely processed.
Solution Approach 2:
The write buffer circuit is divided into two functional components: a store queue for receiving instructions and a combining buffer for holding store release instructions. This segmentation allows different parts of the buffer circuit to perform different functions - the store queue can accept instructions continuously while the combining buffer manages the ordering constraints for store release instructions, thereby maintaining throughput while ensuring correctness.
2Reliability
If store release instructions are delayed until all pending store instructions are committed, then memory consistency is maintained, but pipeline efficiency deteriorates due to empty buffer states
Solution Approach 1:
Store release instructions are launched into the combining buffer preliminarily, before the commit condition is satisfied. This allows the pipeline to remain full and efficient, while the actual write operation is postponed. The combining buffer acts as a holding area that decouples instruction launch from instruction execution timing.
Solution Approach 2:
The combining buffer serves as an intermediary structure between the store queue and the memory write operation. It receives store release instructions from the store queue and holds them until all pending older store instructions are committed, then releases them for processing. This intermediary buffers the timing discrepancy between instruction launch and execution.
3Reliability
If store release instructions are processed sequentially after all pending stores are committed, then ordering semantics are preserved, but write buffer utilization deteriorates due to empty buffer states
Solution Approach 1:
The combining buffer preliminarily accepts and holds store release instructions from the store queue, keeping the write buffer circuit utilized and busy. The instructions are held in the combining buffer until the ordering condition is met, at which point they are processed in the correct order. This maintains both buffer utilization and ordering semantics.
Solution Approach 2:
Multiple store release instructions are combined and held together in the combining buffer until they can be processed. This merging allows the buffer to remain full and utilized, while still maintaining the required ordering semantics by processing all combined instructions only after all pending older store instructions are committed.
Data Source
AI summary
Write buffer circuit supporting store release combining of store operations from a memory access stage of a processor instruction pipeline for efficient processing of store release instructions, and related methods. The write buffer circuit is interfaced with an instruction pipeline of a processor to receive and commit (write data) executed store instructions to memory. The write buffer circuit allows launching of store release instructions from a store queue (STQ) to a write combining buffer (WCB) even if pending, older store instructions are not yet committed to non-cacheable memory. The write buffer circuit is configured to delay release of store release instructions from the WCB for their data to be written to non-cacheable memory until any pending, older store instructions have been committed. This facilitates combining of address related store-release instructions in the WCB that can be written to memory in a single write operation.