Write Combining Buffer for Ordered Store Release Throughput
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Solution Overview
Problem
The use of store release instructions in processor pipelines leads to reduced throughput performance due to the need to delay launching these instructions until all pending, older store instructions have been committed, causing pipeline bubbles and inefficiencies, especially when a large number of such instructions are used.
Innovation Solution
A write buffer circuit that allows store release instructions to be launched to a combining buffer even if there are pending, older store instructions not yet committed, while delaying the release of these instructions for non-cacheable memory until all pending store instructions are committed, enabling combining of multiple store release instructions and avoiding pipeline bubbles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If store release instructions are delayed until all pending older store instructions are committed, then memory ordering correctness is ensured, but processor throughput is reduced due to pipeline bubbles
Solution Approach 1:
The patent segments the store instruction processing into two distinct paths: a fast path for non-release store instructions that can be processed immediately, and a controlled path for store release instructions that require ordering guarantees. This segmentation allows the system to maintain throughput by processing most stores quickly while ensuring correctness only where needed for release instructions.
Solution Approach 2:
The patent introduces a mediator mechanism (the store release combining buffer and associated logic) that sits between the store queue and memory. This intermediary allows store release instructions to be buffered and combined with other store instructions, enabling the system to maintain ordering correctness without immediately blocking the execution of subsequent store release instructions.
2Reliability
If store release instructions are launched only when the combining buffer is empty, then read hazards are avoided, but pipeline bubbles occur and throughput decreases
Solution Approach 1:
The patent applies preliminary action by allowing store release instructions to be launched into the combining buffer even when other store instructions are pending, as long as the combining buffer is not full. This anticipatory approach ensures that store release instructions are prepared in advance for potential combining operations, reducing the need for pipeline bubbles while maintaining read hazard avoidance through controlled release mechanisms.
3Productivity
If a larger store queue size is used to accommodate more store release instructions, then processing capacity increases, but device complexity and resource consumption increase
Solution Approach 1:
The patent merges the processing of multiple store release instructions into a single combining buffer entry by combining them into a batch operation. This allows the system to handle multiple store release instructions without proportionally increasing the store queue size, as the combining mechanism consolidates multiple individual operations into one coordinated memory transaction.
Data Source
AI summary
Write buffer circuit supporting store release combining of store operations from a memory access stage of a processor instruction pipeline for efficient processing of store release instructions, and related methods. The write buffer circuit is interfaced with an instruction pipeline of a processor to receive and commit (write data) executed store instructions to memory. The write buffer circuit allows launching of store release instructions from a store queue (STQ) to a write combining buffer (WCB) even if pending, older store instructions are not yet committed to non-cacheable memory. The write buffer circuit is configured to delay release of store release instructions from the WCB for their data to be written to non-cacheable memory until any pending, older store instructions have been committed. This facilitates combining of address related store-release instructions in the WCB that can be written to memory in a single write operation.