Write Buffer Flash Storage Sequencing to Prevent Threshold Overlap

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current storage devices with flash memories face inefficiencies in executing multiple program operations due to overlapping threshold voltage distributions, which affect data storage and retrieval processes.

Innovation Solution

A storage device with a nonvolatile memory and a write buffer memory that performs sequential program operations on different word line groups, using incremental step pulse programming to narrow threshold voltage distributions and secure delay times between operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple program operations are executed simultaneously in current storage devices, then processing throughput increases, but threshold voltage distributions overlap causing data storage errors

Engineering Contradiction:
Improveprogram operation throughputVSAvoiddata storage accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the program operations into distinct sequential stages (first program operation on first word line group, then second program operation on second word line group) and divides the memory cell array into multiple word line groups. This segmentation prevents threshold voltage overlap by isolating operations in both space (different word line groups) and time (sequential execution), thereby maintaining data storage accuracy while enabling parallel processing of multiple data sets through the write buffer memory.

Inventive Principle:
Principle #1Segmentation

2Reliability

If program operations are performed sequentially to prevent threshold voltage overlap, then data storage reliability improves, but processing speed decreases

Engineering Contradiction:
Improvethreshold voltage distribution separationVSAvoidprogram operation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements continuity of useful action by utilizing the write buffer memory to continuously receive and store incoming data from the host during the execution of program operations. While the storage controller performs sequential program operations on different word line groups to maintain threshold voltage separation, the write buffer memory ensures that data reception and preparation continue without interruption, thereby maximizing system throughput and minimizing idle time.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If a large-capacity write buffer memory is added to store multiple data sets, then efficiency of executing multiple program operations improves, but device complexity increases

Engineering Contradiction:
Improvemulti-program operation efficiencyVSAvoidmemory structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The write buffer memory in the patent serves multiple functions: it stores first data for a first program operation, stores second data for a second program operation, and can buffer data during read operations. This multi-functional design allows the same memory structure to support various operational modes (programming, reading, and data buffering) without requiring separate dedicated memory structures for each function, thereby improving productivity while controlling device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10908842B2Storage device including write buffer memory and method of operating storage device
Publication Date: 2021.02.02 SAMSUNG ELECTRONICS CO LTD
  • US10908842B2 patent drawing
  • US10908842B2 patent drawing
  • US10908842B2 patent drawing

AI summary

A storage device includes a nonvolatile memory including a plurality of nonvolatile memory cells, a write buffer memory storing first data and second data received from a host, and a storage controller storing the first data and the second data that are stored in the write buffer memory into the nonvolatile memory. The storage controller performs a first program operation and a second program operation on a plurality of first memory cells connected to a first word line group to store the first data, and performs a first program operation and a second program operation on a plurality of second memory cells connected to a second word line group to store the second data. While the storage controller performs the first program operation on the plurality of second memory cells, the first data is written in the write buffer memory.