Write Cache Consolidating Host Requests to Reduce Read-Modify-Write Overhead
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Solution Overview
Problem
Current memory sub-systems experience performance degradation due to the need for multiple physical reads and writes during write operations, especially when implementing fault-tolerant redundancy schemes, which increases read-modify-write overhead.
Innovation Solution
The solution involves consolidating host write requests into full stripe writes without evicting the stripe to the memory device, thereby limiting the update and storage of redundancy metadata until after a full stripe write, utilizing a write cache to reduce overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault-tolerant redundancy schemes are implemented with read-modify-write operations, then data reliability is improved, but write operation performance deteriorates due to increased overhead
Solution Approach 1:
The patent applies preliminary action by pre-fetching data blocks that are likely to be modified based on write request patterns, and pre-calculating redundancy metadata for multiple potential write operations. This allows the system to have redundancy metadata ready before actual writes occur, eliminating the need for read-modify-write operations during critical write paths and thus maintaining both reliability and performance
Solution Approach 2:
The patent introduces an intermediary layer (write buffer/cache with pre-calculated redundancy metadata) between the host write requests and the actual storage media. This intermediary maintains fault-tolerant redundancy by pre-calculating metadata for multiple possible writes, allowing writes to proceed without immediate read-modify-write operations, thereby resolving the contradiction between reliability and write performance
2Reliability
If read-modify-write operations are performed for each write request, then data integrity is improved, but the number of physical reads and writes increases
Solution Approach 1:
The system pre-calculates and stores redundancy metadata for multiple potential write operations in advance. When a write request arrives, the pre-calculated metadata is already available, eliminating the need for immediate read-modify-write cycles. This preliminary preparation maintains data integrity while significantly reducing the time required for write operations
Solution Approach 2:
The patent transitions from a single-dimension approach (processing one write request at a time with read-modify-write) to a multi-dimensional approach by pre-calculating redundancy metadata for multiple potential write operations simultaneously. This dimensional expansion allows the system to serve multiple write requests using pre-prepared metadata, reducing overall write operation time while maintaining integrity
3Reliability
If redundancy metadata is updated and stored with each write operation, then fault tolerance is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and caching redundancy metadata for multiple potential write operations before they actually occur. This advance preparation consolidates metadata management into a batch process rather than requiring complex real-time updates for each individual write, thereby maintaining fault tolerance while reducing operational complexity
Solution Approach 2:
The patent merges multiple redundancy metadata update operations into a single consolidated process. By pre-calculating metadata for multiple writes and applying them together, the system maintains fault tolerance across multiple data blocks while simplifying the metadata management process, reducing the complexity associated with handling each write operation individually
Data Source
AI summary
A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.