Write Cache Circuit Shared Storage for Mask Write Area Reduction
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Solution Overview
Problem
The existing memory technologies require separate memory cells for different write modes, such as direct and mask write operations, leading to an increased area of the write circuit, which does not align with current memory development trends.
Innovation Solution
A write cache circuit is introduced, comprising a control circuit and two cache circuits that manage write pointers and output pointers based on write and mask write instructions, allowing for shared storage of write addresses and reducing the layout area by integrating storage spaces for both write and mask write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory cells are configured for different write modes (direct write and mask write), then operational independence between write modes is ensured, but the area of the write circuit is greatly increased
Solution Approach 1:
The patent merges the storage functions for direct write and mask write operations into a single shared memory cell. The control circuit manages write operations by selectively enabling direct write mode or mask write mode, allowing both operations to share the same storage resource while maintaining operational independence through control logic that prevents simultaneous conflicting operations.
Solution Approach 2:
The memory cell is designed to serve multiple functions by supporting both direct write and mask write operations. The control circuit implements multi-functionality by interpreting different write commands and routing them to the same memory cell appropriately, enabling one storage unit to fulfill the roles previously requiring separate dedicated cells for each write mode.
2Adaptability or versatility
If separate memory cells are used for direct write and mask write operations, then different write modes can operate independently, but the layout area of the write cache circuit is increased
Solution Approach 1:
The patent combines the storage resources for direct write and mask write operations into a single shared memory cell, thereby reducing the overall layout area. The control circuit maintains adaptability by implementing logic that selectively activates either direct write or mask write mode based on the operation type, ensuring that both write modes can function independently without requiring separate physical storage cells.
3Reliability
If multiple memory cells are allocated for different write modes, then operational reliability is improved, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by merging the storage functions into a single memory cell while maintaining operational reliability through a control circuit that manages both direct write and mask write operations. The control logic ensures reliable operation by preventing simultaneous conflicting writes and properly routing control signals for each operation type to the shared memory cell.
Solution Approach 2:
The write circuit achieves multi-functionality by using a single memory cell to handle both direct write and mask write operations. The control circuit implements universal control logic that can interpret and execute different types of write commands, reducing the need for separate dedicated circuit paths while maintaining the reliability and independence of each write mode through proper signal management.
Data Source
AI summary
The present disclosure provides a write cache circuit, a data write method, and a memory. The write cache circuit includes: a control circuit configured to generate, on the basis of a mask write instruction, a first write pointer and a pointer to be positioned, generate a second write pointer on the basis of a write command, generate a first output pointer on the basis of a mask write shift instruction, and generate a second output pointer on the basis of a write shift instruction; a first cache circuit configured to cache, on the basis of the first write pointer, the pointer to be positioned and output a positioned pointer on the basis of the first output pointer, the positioned pointer being configured to instruct a second cache circuit to output a write address written by the second write pointer generated according to the mask write instruction.