Write Cleaner Circuit for Write-Back Cache Memory Coherency
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Solution Overview
Problem
Write-back (WB) cache memories in computing systems face inefficiencies when handling sequential memory write transactions, leading to incoherency between cache and system memory, which results in random updates to system memory, increasing power consumption and latency due to unnecessary pre-charging of DRAM cells.
Innovation Solution
A write cleaner circuit is introduced to enable write-through functionality by explicitly cleaning cache lines and updating system memory during write transactions, allowing for simultaneous updates of cache and system memory, reducing the need for random updates and minimizing pre-charging events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If write-back cache memory is used to improve system performance, then cache write speed is improved, but system memory coherency deteriorates leading to random updates
Solution Approach 1:
The patent applies preliminary action by proactively identifying sequential write transactions and issuing clean requests before cache lines are evicted. The write cleaner circuit detects sequential addresses and preemptively updates system memory, preventing coherency issues before they occur. This resolves the contradiction by maintaining coherency through advance action while preserving write-back performance.
Solution Approach 2:
The patent implements feedback through the write cleaner circuit that continuously monitors cache write transactions, detects sequential address patterns, and responds by generating clean requests. This feedback loop ensures system memory is updated appropriately for sequential writes while leaving random writes to follow traditional write-back behavior, thus maintaining coherency without sacrificing performance.
2Adaptability or versatility
If dirty cache lines are evicted randomly in write-back cache, then cache flexibility is improved, but power consumption increases due to unnecessary pre-charging
Solution Approach 1:
The write cleaner circuit performs preliminary action by detecting sequential write patterns and proactively cleaning cache lines before eviction. This allows the system to maintain write-back cache flexibility while avoiding unnecessary pre-charging of DRAM cells, as memory updates are coordinated for sequential accesses. The principle resolves the contradiction by enabling advance planning of memory updates.
Solution Approach 2:
The patent changes the state parameter of cache lines from dirty to clean proactively for sequential writes. By changing the cache line state before eviction, the system可以避免 unnecessary DRAM pre-charging operations, reducing power consumption while maintaining cache flexibility for both sequential and random workloads.
3Productivity
If system memory is updated on cache eviction, then write-back performance is maintained, but latency increases for sequential writes
Solution Approach 1:
The patent merges the write operation with the clean operation for sequential addresses. When sequential writes are detected, the clean request is issued immediately alongside the write, combining two separate operations into one coordinated action. This reduces latency by eliminating the need to wait for cache eviction before updating system memory, while maintaining write-back performance for non-sequential operations.
Solution Approach 2:
The write cleaner circuit performs preliminary action by issuing clean requests immediately when sequential writes are detected, rather than waiting for cache eviction. This preliminary update of system memory reduces latency for sequential writes while preserving the performance benefits of write-back caching for other workloads.
Data Source
AI summary
A write cleaner circuit can be used to implement write-through (WT) functionality by a write-back (WB) cache memory for updating the system memory. The write cleaner circuit can intercept memory write transactions issued to the WB cache memory and generate clean requests that can enable the WB cache memory to send update requests to corresponding memory locations in the system memory around the same time as the memory write transactions are performed by the WB cache memory, and clear dirty bits in the cache lines corresponding to those memory write transactions.