Write Clock Phase Estimation for Bit-Patterned Media

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Solution Overview

Problem

Bit-patterned media recording systems face challenges in write clock synchronization, leading to misalignment and writing errors due to deviations in frequency and phase of the write clock, which are difficult to detect and correct, especially in discontinuous island-based patterns.

Innovation Solution

A write clock synchronization system that includes a channel module to read servo sectors, a sampling module to generate samples based on servo and write clocks, and an adjustment module to estimate and adjust the phase of the write clock signal, ensuring precise alignment with bit islands, thereby preventing writing over non-magnetic areas between islands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If bit-patterned media recording systems use discontinuous island-based patterns to increase storage capacity, then storage density is improved, but write clock synchronization becomes more difficult leading to misalignment and writing errors

Engineering Contradiction:
Improvestorage capacityVSAvoidwrite clock synchronization accuracy
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The system performs preliminary sampling of the write clock signal during a calibration phase before actual data writing. This preliminary action captures the write clock phase information in advance, allowing the system to compensate for frequency and phase deviations before they cause misalignment during data writing operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback mechanism where the sampled write clock signal is compared against the ideal clock signal, and the detected phase and frequency deviations are fed back to adjust the write head positioning and timing. This closed-loop feedback ensures continuous synchronization between the write clock and the bit island positions.

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If the write clock frequency and phase deviate from ideal values, then writing flexibility is improved, but alignment with bit islands deteriorates causing writing errors

Engineering Contradiction:
Improvewriting flexibilityVSAvoidbit island alignment accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The system dynamically changes the write clock parameters (frequency and phase) based on real-time detection. By adjusting these parameters to match the actual write clock signal characteristics, the system maintains alignment accuracy with bit islands while accommodating variations in writing conditions and media properties.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system transitions from a static write clock approach to a dynamic one where the write clock parameters are continuously adjusted based on detected deviations. This dynamic adaptation allows the system to maintain precise alignment with bit islands despite changes in operating conditions, media properties, or head positioning variations.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If conventional continuous media recording methods are used, then device complexity is reduced, but storage capacity is limited compared to bit-patterned media

Engineering Contradiction:
Improverecording system simplicityVSAvoidstorage capacity
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The system introduces an intermediary calibration and detection phase that bridges the gap between simple continuous media recording and complex bit-patterned media recording. This intermediary process samples the write clock signal and determines phase information, enabling the system to handle bit-patterned media with increased storage capacity while managing complexity through a structured two-phase approach.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8755139B1System with servo clock and write clock based phase estimation for discontinuous media writing
Publication Date: 2014.06.17 MARVELL ASIA PTE LTD
  • US8755139B1 patent drawing
  • US8755139B1 patent drawing
  • US8755139B1 patent drawing

AI summary

A system including a storage device, a channel module, a sampling module, a first phase module, and an adjustment module. The storage device includes servo sectors, and discontinuous media with bit islands. The channel module reads the servo sectors based on a servo clock to generate an analog signal. The sampling module samples the analog signal based on a servo clock signal to generate first samples, and based on a write clock signal to generate second samples. The first phase module estimates a phase of the write clock signal based on the first samples, and the second samples. The adjustment module adjusts the phase of the write clock signal based on the estimated phase of the write clock signal. The channel module, based on the write clock signal with the adjusted phase, writes data to the bit islands of the discontinuous media.