Differential Write Clock Phasing to Avoid Memory Metastability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems face challenges in maintaining high data transfer rates while minimizing power consumption, particularly when resuming write clock signaling, which can lead to metastable states and increased latency.
Innovation Solution
The use of multiple differential write clock signals with different phases, such as a 90-degree phase offset, allows memory devices to avoid metastable states without introducing additional latency, by referencing these signals transmitted by the memory controller, thereby eliminating the need for components like clock divider circuits that may enter metastable states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single write clock signal is used to synchronize memory operations, then the system structure is simple, but metastable states occur when resuming clock signaling causing increased latency
Solution Approach 1:
The single write clock signal is segmented into multiple differential write clock signals with different phases (e.g., first and second phases). This segmentation allows the memory device to avoid metastable states by providing multiple reference points for synchronization, thereby reducing latency when resuming clock signaling without significantly increasing system complexity.
Solution Approach 2:
The solution introduces a phase dimension to the clock signaling system. By adding phase differentiation (e.g., 0度和180度相位差) to the temporal dimension of clock signals, the system gains an additional degree of freedom for synchronization, enabling faster recovery from metastable states while maintaining structural simplicity.
2Use of energy by stationary object
If clock divider circuits are used to generate write clock signals, then the system can operate at different frequencies, but the circuits may enter metastable states increasing power consumption
Solution Approach 1:
The patent extracts and eliminates the clock divider circuit from the memory device by providing the write clock signal directly from the memory controller. This removal eliminates the metastable state susceptibility inherent in clock divider circuits while maintaining the ability to operate at different frequencies, thereby reducing power consumption and improving reliability.
Solution Approach 2:
The memory controller acts as an intermediary that generates and transmits the differential write clock signals directly to the memory device. This intermediary approach replaces the need for internal clock divider circuits in the memory device, eliminating their metastable state issues and associated power consumption while maintaining frequency control capabilities.
3Productivity
If high data transfer rates are maintained, then processing speed is improved, but power consumption increases due to continuous clock signaling
Solution Approach 1:
The system uses periodic clock signaling where the memory controller transmits differential write clock signals only when data transfer is required. The clock signaling can be suspended or reduced when idle, allowing the system to maintain high data transfer rates during active operations while reducing power consumption during idle periods through periodic rather than continuous operation.
Data Source
AI summary
Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (e.g., of a host device) can provide two differential write clock signals to a memory device over an interconnect. The two differential write clock signals may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device can use the multiple differential write clocks signals provided by the memory controller to process memory requests.