Write Combine Buffer Using Physical Address Proxies
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Solution Overview
Problem
Cache memories in microprocessors face challenges in reducing access time and improving cache coherency, particularly in multi-processor systems, where the overhead of cache coherence protocols and the physical size of cache structures impact processor performance.
Innovation Solution
A microprocessor with a physically-indexed, physically-tagged second-level set-associative cache and a write-combine buffer that uses physical address proxies to efficiently manage cache coherence and combine write operations, reducing the need for extensive cache coherence-related information and optimizing cache access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memory capacity is increased to improve hit rate, then cache hit rate is improved, but physical size of cache increases
Solution Approach 1:
The patent uses physical address proxies (PAPs) as simplified copies of full physical addresses in the write combine buffer. Instead of storing complete physical addresses, the cache stores compressed proxy representations that capture essential addressing information, reducing the space required per entry while maintaining cache functionality and hit rate.
Solution Approach 2:
The patent changes the parameter representation from full physical addresses to compressed physical address proxies. This parameter transformation reduces the bit width required to represent each address, thereby decreasing the physical size of cache structures while preserving the ability to achieve high hit rates through efficient address matching.
2Reliability
If cache coherence protocol information is extended to ensure coherency, then cache coherency is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential coherence information needed from full physical addresses by using physical address proxies. The PAPs capture the critical portions of addresses required for coherence checking without including all the detail present in complete physical addresses, thereby reducing protocol complexity while maintaining coherency guarantees.
Solution Approach 2:
The physical address proxy acts as an intermediary between full physical addresses and cache coherence protocols. It serves as a simplified representation that enables coherence checking and protocol operation without requiring the complexity of handling complete physical addresses throughout the coherence protocol machinery.
3Measurement precision
If write combine buffer uses full physical addresses, then address precision is improved, but loss of time in write operations increases
Solution Approach 1:
The patent performs preliminary compression of physical addresses into proxies when entries are placed in the write combine buffer. This preliminary action transforms addresses to their compact PAP representation upfront, enabling faster subsequent operations without sacrificing the precision needed for correct address matching and coherence verification.
Solution Approach 2:
The physical address proxy serves as a compact copy of the full physical address that retains sufficient precision for write combine operations. This copied representation is more efficient to process and compare, reducing the time required for write operations while maintaining the address precision necessary for correct memory semantics.
Data Source
AI summary
A microprocessor includes a physically-indexed-and-tagged second-level set-associative cache. Each cache entry is uniquely identified by a set index and a way number. Each entry of a write-combine buffer (WCB) holds write data to be written to a write physical memory address, a portion of which is a write physical line address. Each WCB entry also holds a write physical address proxy (PAP) for the write physical line address. The write PAP specifies the set index and the way number of the cache entry into which a cache line specified by the write physical line address is allocated. In response to receiving a store instruction that is being committed and that specifies a store PAP, the WCB compares the store PAP with the write PAP of each WCB entry and requires a match as a necessary condition for merging store data of the store instruction into a WCB entry.