Write Command-Data Timing Circuit for Memory Clock Synchronization
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Solution Overview
Problem
High-speed memory clock signals in semiconductor memory systems face challenges in optimizing write throughput due to varying propagation delays caused by power, voltage, and temperature conditions, which complicates the timing of internal write operations and requires tight phase control between memory and write clocks.
Innovation Solution
A write command-data timing circuit that includes a memory clock and command buffer, a write clock buffer, and a multi-phase clock generator to synchronize and delay signals, allowing for correct timing of write operations by approximating propagation delays and generating internal clock signals that account for write latency, thereby synchronizing clock signals across different domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional modeling of write clock path and system clock path with same propagation delay is used, then timing simplicity is maintained, but write throughput cannot be optimized and timing accuracy deteriorates due to varying propagation delays
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing propagation delay values in lookup tables before actual write operations occur. The system measures propagation delays under various power, voltage, and temperature conditions beforehand, then uses these pre-computed values to accurately time write operations without real-time calculation overhead, thereby optimizing write throughput while maintaining timing accuracy.
Solution Approach 2:
The patent changes parameters by using multiple propagation delay values corresponding to different power, voltage, and temperature conditions. Instead of assuming a fixed propagation delay, the system selects appropriate delay values from lookup tables based on current operating conditions, enabling accurate timing across varying environmental parameters while maintaining high write throughput.
2Manufacturing precision
If propagation delay variations due to power, voltage, and temperature conditions are accounted for, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses copying by creating lookup tables that store pre-measured propagation delay values for different operating conditions. Instead of implementing complex real-time measurement and calculation circuits, the system copies pre-computed delay values from lookup tables based on current power, voltage, and temperature conditions, simplifying the control logic while maintaining high timing accuracy.
Solution Approach 2:
The system performs preliminary measurements of propagation delays under various power, voltage, and temperature conditions during manufacturing or initialization, storing these values in lookup tables. This preliminary action eliminates the need for complex real-time measurements during operation, reducing device complexity while ensuring accurate timing compensation for propagation delay variations.
3Reliability
If tight phase control between memory clock and write clock is implemented, then correct operation is achieved, but device complexity and control difficulty increase
Solution Approach 1:
The patent applies preliminary action by pre-determining the relationship between memory clock and write clock phases under various operating conditions. The system stores phase relationship data in lookup tables based on power, voltage, and temperature conditions, allowing the controller to directly retrieve appropriate phase settings without implementing complex real-time phase control circuits, thereby maintaining reliable operation while reducing device complexity.
Solution Approach 2:
The system changes phase control parameters by selecting from multiple pre-determined phase relationships stored in lookup tables, corresponding to different power, voltage, and temperature conditions. This approach replaces complex continuous phase control with discrete parameter selection, maintaining correct operation across varying conditions while simplifying the control mechanism.
Data Source
AI summary
Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.