Write Control Signal Generation Circuit for DRAM Test Channel Optimization
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Solution Overview
Problem
Conventional test equipment for high-frequency DRAM devices is inefficient due to limited usable channels, leading to increased test time and cost, as it struggles to simultaneously test multiple parameters effectively with high-frequency clock signals.
Innovation Solution
A write control signal generation circuit that includes a delay/comparison/transmission block and a control signal generation unit, which generates a write control signal by delaying the write command signal based on a test mode signal and mode control signal, allowing for parallel data transmission synchronized with a low-frequency reference clock, thereby matching data transmission speed with the write control signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-frequency clock signals are used for testing DRAM devices, then the memory apparatus can be tested at its operating frequency, but the number of usable test channels is limited
Solution Approach 1:
The patent changes the frequency parameter of the clock signal used for data transmission. Specifically, it uses a low-frequency clock signal (with period at least twice that of the high-frequency clock) for transmitting data bits, while the high-frequency clock is used for the write control signal. This parameter change allows the test equipment to operate multiple channels simultaneously without interference, resolving the channel limitation while maintaining test accuracy through proper timing synchronization.
2Adaptability or versatility
If a lower frequency clock signal is used for data transmission, then more test channels can be used simultaneously, but the data transmission speed does not correspond to the clock speed
Solution Approach 1:
The patent applies preliminary action by using a delay/comparison/transmission block that delays the write command signal by a predetermined period. This delay ensures that the write control signal is generated at the appropriate time to match the slower data transmission speed caused by the low-frequency clock. By pre-adjusting the timing of control signals, the system synchronizes data and control signal transmission, maintaining effective data transmission despite the reduced clock frequency.
3Loss of time
If conventional test equipment is used with limited channels, then test time increases, but replacing equipment is costly
Solution Approach 1:
The patent makes the test equipment more versatile by enabling it to handle multiple test channels simultaneously using low-frequency clock signals. The write control signal generation circuit can manage multiple data streams from different channels without requiring additional high-frequency clock channels. This multi-functionality allows conventional equipment to test multiple parameters and products concurrently, reducing test time without the need for expensive equipment replacement.
Data Source
AI summary
A write control signal generation circuit includes a delay/comparison/transmission block that outputs one of a delayed write command signal and a write command signal according to a test mode signal, and a control signal generation unit that generates a write control signal by delaying the output of the delay/comparison/transmission block corresponding to a variable amount of delay.