Write Conversion Latch Circuit for Compressed Memory Writes
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Solution Overview
Problem
Existing data input/output circuits in memory technologies face challenges in efficiently managing data write modes, particularly in integrating compressed write data without affecting the transmission time of primary data.
Innovation Solution
The proposed write conversion circuit includes a first latch circuit with three input terminals, where the first input terminal receives the primary data, the second input terminal receives a signal generated based on secondary data, and the third input terminal receives an inverted signal of a compressed write mode identification signal. The control terminal receives a second identification signal, determining the data write mode and enabling the circuit to output either the primary or secondary data without additional devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional devices are added to integrate compressed write data, then the functionality is improved, but the device complexity increases
Solution Approach 1:
The latch circuit is designed to perform multiple functions: it can operate in normal write mode to write first data, in compressed write mode to write second data, and in pass-through mode to transmit first data without writing. This multi-functionality is achieved through control signals (first identification signal and second identification signal) that configure the same circuit structure to handle different data write modes, eliminating the need for separate dedicated circuits for each mode.
Solution Approach 2:
The latch circuit dynamically switches between different operational modes based on control signals. The circuit structure remains fixed, but its functional behavior changes dynamically according to the states of the first identification signal (indicating compressed write mode) and second identification signal (indicating write or pass-through mode), allowing the same hardware to adapt to different data integration requirements without physical reconfiguration.
2Adaptability or versatility
If additional data paths are created for secondary data, then the data integration capability is improved, but the chip area increases
Solution Approach 1:
The same data path and latch circuit infrastructure is used for both first data and second data transmission. The circuit dynamically configures itself based on control signals to handle different data types, eliminating the need for separate dedicated data paths for compressed write data. This shared infrastructure reduces chip area while maintaining full data integration capability.
Solution Approach 2:
The patent merges the transmission paths for first data and second data into a single shared path. The latch circuit combines multiple data sources (first data from first input terminal, second data from second input terminal) and routes them through common output infrastructure, controlled by identification signals. This consolidation eliminates redundant data paths and reduces overall chip area.
3Adaptability or versatility
If the circuit structure is expanded to handle both data modes, then the functionality is improved, but the manufacturing complexity increases
Solution Approach 1:
The latch circuit is designed as a universal building block that can be manufactured once and then configured through control signals to perform different functions. The same physical circuit structure handles normal write operations, compressed write operations, and pass-through operations, simplifying the manufacturing process compared to producing separate dedicated circuits for each mode.
Solution Approach 2:
The circuit's operational parameters are changed through control signals rather than through physical manufacturing variations. The first identification signal and second identification signal modify the circuit's behavior parameters (which data to write, which mode to operate in) without requiring different physical circuit structures, thereby simplifying manufacturing while maintaining functional versatility.
Data Source
AI summary
The write conversion circuit includes a first latch circuit, provided with a first input terminal, a second input terminal, a third input terminal, a control terminal, and an output terminal. The first input terminal receives first data, the second input terminal receives a first input signal, with the first input signal being generated based on second data, the third input terminal receives an inverted signal of a first identification signal, and the control terminal receives a second identification signal. The first latch circuit is used to select and output either the first data or the second data based on the second identification signal. The first identification signal is an identification signal of a compressed write mode; the second identification signal and the first identification signal together determine a data write mode of the first latch circuit, which includes the compressed write mode and a normal write mode.