Write Destage Scheduling Algorithm for Storage Cache

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Solution Overview

Problem

Current data storage systems face challenges in optimizing the scheduling of write requests from cache memory, particularly with increased devices per spindle, message bus usage, and the need for parity RAID protection, leading to unpredictable and prolonged host I/O response times.

Innovation Solution

Implementing a scheduling algorithm that enforces a target minimum number of write destages per unit time, prioritizing write requests based on elapsed time and pending writes, and adjusting priorities dynamically to ensure timely processing and maintain performance predictability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If prior art algorithms schedule write destages based on threshold numbers or fixed percentages of operation time, then the scheduling is simple to implement, but the host I/O response times become unpredictable and prolonged

Engineering Contradiction:
Improvehost I/O response timeVSAvoidunpredictable response time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic scheduling that adapts to current system conditions rather than using fixed thresholds or percentages. The scheduler continuously monitors write request characteristics, cache state, and device performance to adjust destage timing and priority, ensuring optimal response times under varying workloads while maintaining predictable performance guarantees.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms that monitor actual destage performance and host I/O response times, using this information to adjust scheduling decisions. The scheduler receives feedback about cache occupancy, write request patterns, and device utilization to dynamically optimize destage operations, transforming the open-loop fixed-threshold approach into a closed-loop adaptive system.

Inventive Principle:
Principle #23Feedback

2Speed

If read requests are assigned higher priority than write requests, then read performance is improved, but write destage performance deteriorates

Engineering Contradiction:
Improveread request performanceVSAvoidwrite destage performance
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent implements dynamic priority adjustment for write requests based on real-time conditions. Rather than statically prioritizing reads over writes, the system evaluates factors such as write request age, cache occupancy, device utilization, and service level agreements to dynamically adjust write priority, allowing the system to maintain read performance while preventing write starvation and improving overall write destage performance.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the priority parameter of write requests dynamically based on multiple conditions including elapsed time since write arrival, current cache occupancy, device utilization metrics, and configured performance targets. This multi-parameter adjustment mechanism allows flexible balancing between read and write performance without fixed hierarchical constraints.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If multiple devices are added per spindle to increase capacity, then storage capacity increases, but scheduling complexity and I/O response time variability increase

Engineering Contradiction:
Improvestorage capacityVSAvoidscheduling complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the scheduling domain into device-specific queues and individual request tracks, allowing independent management of each device's write requests. This segmentation enables the scheduler to handle multiple devices per spindle without exponential complexity growth, as each device is managed separately with its own performance targets and scheduling decisions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system uses dynamic scheduling that adapts to the actual state of each device and request rather than following fixed complex algorithms. By continuously monitoring device utilization, request characteristics, and performance metrics, the scheduler dynamically adjusts destage timing and priority, simplifying the scheduling logic while maintaining optimal performance across multiple devices per spindle.

Inventive Principle:
Principle #15Dynamics

4Productivity

If write requests are held in cache longer to batch destages, then destage efficiency improves, but host I/O response time increases

Engineering Contradiction:
Improvedestage efficiencyVSAvoidhost I/O response time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic destage timing that adapts to individual write request characteristics and system state. Rather than holding all writes in cache for extended batching, the scheduler dynamically determines optimal destage timing based on request age, size, priority, cache occupancy, and device utilization, achieving efficient batching when beneficial while preventing excessive delays that would harm response time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes multiple parameters including destage threshold, batching window, and priority levels based on real-time conditions. When cache occupancy is high or device utilization is low, the system increases batching aggressiveness; when response time requirements tighten or cache is full, it reduces batching and performs more frequent destages, dynamically optimizing the trade-off between destage efficiency and response time.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7577787B1Methods and systems for scheduling write destages based on a target
Publication Date: 2009.08.18 EMC IP HLDG CO LLC
  • US7577787B1 patent drawing
  • US7577787B1 patent drawing
  • US7577787B1 patent drawing

AI summary

Methods and systems are disclosed that relate to scheduling the processing of I/O requests in a cache for a plurality of logical devices associated with the cache. An exemplary method includes identifying a minimum target number of write destages to be performed with respect to a logical device per unit time. In identifying the minimum target number, factors such as a write pending count and an average queue length of writes pending may be considered. The method further includes enforcing the target minimum number of write destages. A disclosed method of enforcing the target includes tracking the number of write destages performed on the logical device and increasing a priority for a write request to the logical device when the minimum target number of write destages is not met.