Write Detect Circuitry for Non-Volatile Memory Stress Mitigation
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Solution Overview
Problem
Non-volatile resistive memory arrays face stress issues during write operations due to high currents induced by permanently blown resistive cells, which can lead to reliability limits and device failure, especially during one-time programmable (OTP) writes.
Innovation Solution
Incorporation of write detect circuitry using a self-referencing scheme, specifically employing a sample and hold circuit and sense amplifiers to detect the blown resistance state, allowing the circuit to stop the write operation and prevent further writes to the blown cell, thereby mitigating stress on the memory array and periphery circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a destructive write operation is performed to fuse a bit cell into a permanent shorted state, then the data storage function is achieved, but the bit cell and periphery circuitry experience increased stress that can lead to device failure
Solution Approach 1:
The patent implements a write detect circuit that continuously monitors the resistance state of the selected bit cell during write operations. When the cell reaches the desired fused state (detected through resistance threshold comparison), the circuit provides feedback to stop further write current application, preventing excessive stress accumulation in the bit cell and periphery circuitry.
Solution Approach 2:
The write detect circuit performs preliminary detection of the bit cell state during the write operation sequence. By detecting the blown state early in the write process and halting subsequent write cycles to the same cell, the system prevents redundant stress application that would occur without this preliminary detection mechanism.
2Reliability
If write detect circuitry is added to prevent stress during write operations, then device reliability is improved, but circuit complexity increases
Solution Approach 1:
The write detect circuit is designed to serve multiple functions: it detects the blown state during write operations, provides feedback to prevent excessive stress, and can potentially be reused or integrated with existing sense amplifier circuits in the memory architecture. This multi-functionality reduces the overall complexity increase compared to dedicated single-purpose circuits.
Solution Approach 2:
The patent integrates the write detect functionality with existing memory circuit components, particularly merging the detection logic with sense amplifier structures and control circuitry that already exist in the memory array. This consolidation approach minimizes the additional complexity by reusing existing hardware resources rather than adding completely separate detection systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The write detect circuitry effectively prevents excessive stress on the memory array by detecting the blown state during OTP writes and halting the write current, ensuring the reliability of the resistive memory cells and extending their lifespan.
Implementation Method 1
The resistive storage element of a reprogrammable resistive cell can be placed into the HRS or the LRS based on a direction of a write current through the resistive storage element, while the resistive storage element in an OTP resistive cell can either be in a permanently blown state due to a high write current through the resistive storage element or in a non-blown state
Data Source
AI summary
A non-volatile memory includes resistive cells, write circuitry, and write detect circuitry. Each resistive cell has a resistive storage element and is coupled to a corresponding first column line and corresponding second column line. The write circuitry is configured to provide a write current through a resistive storage element of a selected resistive memory cell during a write operation based on an input data value. The write detect circuitry is configured to generate a reference voltage using a voltage at the corresponding first column line coupled to the selected resistive memory cell at an initial time of the write operation, and, during the write operation, after the initial time, provide a write detect signal based on a comparison between the voltage at the corresponding first column line coupled to the selected resistive memory cell and the reference voltage, wherein the input data value is based on the write detect signal.