Write DLL Circuitry for Memory Write Leveling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in accurately timing data strobes due to inherent errors in coarse write leveling processes, which are exacerbated by power bus noise and temperature drift, leading to inefficiencies in data capture and increased error sensitivity.
Innovation Solution
The implementation of a write delay lock loop (WrDLL) circuitry that reduces or eliminates the coarse write leveling stage, synchronizing the internal write signal with external clock phases to align with external DQS voltage and temperature variations, thereby reducing training errors and maintaining timing hand-shaking margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-stage write leveling (coarse and fine) is used to achieve high accuracy in data strobe timing, then manufacturing precision is improved, but loss of time increases due to the extended training process
Solution Approach 1:
The patent applies preliminary action by performing write leveling training during the manufacturing process before the memory device is deployed. The training results are stored in non-volatile memory, allowing the device to skip the time-consuming coarse write leveling stage during operation. This pre-performed calibration eliminates the need for repeated multi-stage training, thus reducing operational time while maintaining high timing accuracy.
2Ease of operation
If coarse write leveling is performed to establish initial timing, then ease of operation is improved, but measurement precision deteriorates due to inherent errors and sensitivity to power bus noise and temperature drift
Solution Approach 1:
The patent segments the write leveling process into two distinct phases: a coarse write leveling stage performed during manufacturing to establish initial timing, and a fine write leveling stage that refines the timing with higher precision. By separating these functions and storing coarse results in non-volatile memory, the system achieves both operational simplicity and measurement precision, as the fine tuning stage can focus solely on high-precision adjustment without being burdened by the initial coarse alignment.
3Adaptability or versatility
If traditional multi-stage write leveling is used, then adaptability to different timing conditions is improved, but device complexity increases due to multiple training stages and error correction mechanisms
Solution Approach 1:
The patent reduces device complexity by performing the complex coarse write leveling calibration during manufacturing and storing the results in non-volatile memory. This preliminary action eliminates the need for complex real-time coarse adjustment circuitry during operation. The device maintains adaptability through the fine write leveling stage, which uses simpler circuitry to refine timing based on the pre-established coarse alignment, thus reducing overall device complexity while preserving timing negotiation flexibility.
Data Source
AI summary
A host device and memory device perform internal write leveling of a data strobe with a write command. The memory device includes an input-output interface that receives the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal. The internal write circuitry includes an emulation loop configured to emulate circuitry in a clock path of a write clock generated from the clock and used to generate a feedback clock. The internal write circuitry includes a write delay lock loop configured to receive the write clock and the feedback clock to determine a number of cycles used for the loop, transmit the number of cycles to the host device to be used as a cycle adjust in an internal write leveling process, and complete the internal write leveling process with the host device using the cycle adjust.