Write Driver Level Shifter Shared Transistors Low Voltage
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Solution Overview
Problem
SRAM circuits face limitations in write margin and operational speed when operating at low power supply voltage due to dummy read occurrences, which affect the capability to overwrite logic values on data lines during write operations.
Innovation Solution
A column driving circuit with cross-coupled pulling devices that are deactivated based on to-be-written data to avoid current fighting, and function as level shifters to accommodate different voltage swings, allowing for efficient write operations without dummy read issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the word line is activated early to enable switches for data writing, then the memory cell becomes accessible for write operation, but a dummy read occurs that transfers previously stored data to the data lines, requiring additional logic value overwriting that limits write margin and speed
Solution Approach 1:
The patent applies preliminary anti-action by deactivating the pulling devices before the dummy read can corrupt the data lines. The control circuit detects the write operation timing and proactively turns off the pulling devices to prevent the harmful effect of current fighting and logic value corruption that would otherwise occur during the dummy read phase.
Solution Approach 2:
The patent implements preliminary action by preparing the pulling devices for deactivation in advance of the dummy read occurrence. The control circuit is configured to deactivate the pulling devices based on the timing of the write operation, ensuring they are already off before the dummy read transfers data to the lines, thus preventing the need for subsequent logic value overwriting.
2Stability of the object's composition
If pulling devices remain active during write operation to maintain data line voltage levels, then voltage stability is improved, but current fighting occurs with activated switches that slows down write operation and reduces operational speed
Solution Approach 1:
The patent applies dynamics by making the pulling devices dynamically controllable rather than statically active. The control circuit adjusts the state of the pulling devices based on the operational phase: deactivating them during write operations to enable fast switching, and activating them during idle phases to maintain voltage stability on the data lines, thus optimizing both speed and stability at different times.
3Reliability
If additional transistors are added to prevent dummy read effects, then write margin is improved, but device complexity and area increase
Solution Approach 1:
The patent implements multi-functionality by designing the existing pulling devices to serve dual purposes: they function as voltage stabilizers during read operations and as controllable switches during write operations. The control circuit enables these devices to be deactivated during writes, allowing the same hardware structures to support both read and write operations without requiring additional dedicated transistors for write protection.
Data Source
AI summary
A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.