Write-Gated CAS Latency Counter Control for DDR2 SDRAM
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Solution Overview
Problem
In DDR2 SDRAM and higher memory devices, the introduction of additive latency (AL) and write latency (WL) leads to increased current consumption due to unnecessary operation of the CAS latency counter during read operations, despite efforts to reduce power consumption by stopping counters during idle states.
Innovation Solution
A counter control signal generating circuit that determines the operation of the CAS latency counter based solely on write commands, independent of read commands, ensuring the counter is stopped only by the final write command, thereby preventing unnecessary current consumption during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CAS latency counter operates during read operations to control AL and WL, then the read and write command input positions can be freely determined, but current consumption increases due to unnecessary counter operation
Solution Approach 1:
The patent applies dynamics by making the counter operation state changeable based on command type. The control signal generator dynamically adjusts the counter enable signal CLKCTL according to whether a read or write command is detected, allowing the system to switch between operational modes (counter running or stopped) to optimize energy consumption while maintaining command flexibility
2Use of energy by moving object
If the counter operation is stopped when all banks are in precharged state (idle state), then current consumption is reduced, but the CL counter still operates unnecessarily during read operations
Solution Approach 1:
The patent inverts the conventional approach by not stopping the counter during read operations but instead preventing read operations from occurring when the counter is already running for write operations. The control signal generator detects write commands and maintains counter operation, while the address latch and counters are designed to handle command sequencing such that read commands are processed only when appropriate, eliminating unnecessary counter operation energy waste
3Use of energy by moving object
If the counter control signal is disabled during read operations, then current consumption is reduced, but the counter may be abnormally stopped when write commands are successively input
Solution Approach 1:
The patent applies feedback by continuously monitoring the command type through the control signal generator, which receives command signals and determines whether to enable or disable counter operation. This feedback mechanism ensures that the counter is stopped during read operations to save energy but remains operational during write operations, preventing abnormal stopping and ensuring reliable counter function throughout the operation sequence
Data Source
AI summary
A counter control signal generating circuit is disclosed. The circuit includes a first counter configured to receive a latched external address, and count the latched external address for a first latency, thereby generating a first counted address, a second counter for counting the first counted address for a second latency, thereby generating a second counted address, a counter control signal generator configured to receive a write recognition signal, which is enabled in response to a write command, and generate a counter control signal for controlling enabling of the second counter, in response to the write recognition signal, a first detecting signal generator configured to receive the write recognition signal, generate a first command signal obtained after counting of the write recognition signal for the first latency, and generate a first detecting signal, which is enabled in response to the write recognition signal, and a second detecting signal generator configured to receive the first command signal, generate a second command signal obtained after counting of the first command signal for the second latency, and generate a second detecting signal, which is enabled in response to the first command signal.