Write Leveling Circuit for Memory Timing Skew Control
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Solution Overview
Problem
As semiconductor memory devices increase in speed and are scaled down, timing issues with signal exchange become critical, particularly in write operations, where the ability to adjust signal timing using write leveling operations is limited by structural characteristics and Process, Voltage, Temperature (PVT) variations, leading to potential calibration failures in memory systems.
Innovation Solution
A write leveling control method that registers data-related signal reference delay values for different memory modules, detects timing skews, and adjusts signal delays based on these values to ensure proper synchronization of clock and data strobe signals, using a leveling reference table and management circuit to stabilize write operations across various memory types and topologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If write leveling operation is performed to adjust signal timing, then timing synchronization between clock signal and data strobe signal is improved, but the ability to adjust signal timing is curtailed as operating frequency increases
Solution Approach 1:
The patent applies preliminary action by performing write leveling calibration during an initial calibration operation at lower frequencies, before the system operates at high frequencies. The calibration operation adjusts signal timing in advance when the system is still stable, storing the optimized timing parameters for use during high-speed operation. This resolves the contradiction by establishing timing synchronization before the frequency increase that would otherwise limit adjustment capability.
Solution Approach 2:
The patent implements dynamics by enabling the memory controller to dynamically adjust signal timing parameters based on detected timing skews during operation. The system continuously monitors the timing relationship between clock and data strobe signals and modifies delay values in real-time, allowing adaptation to varying operating conditions including frequency changes, thereby maintaining timing synchronization without being curtailed by frequency increases.
2Reliability
If calibration operation is performed to stabilize write operation, then timing skew is reduced, but calibration may fail due to PVT variation
Solution Approach 1:
The patent applies feedback by implementing a detection operation that continuously monitors timing skews between clock and data strobe signals during write operations. The memory controller measures the actual timing differences and uses this feedback information to adjust delay values dynamically. This closed-loop approach compensates for PVT variations by adapting to actual operating conditions rather than relying on fixed pre-calibrated values, thereby maintaining calibration accuracy despite environmental changes.
Solution Approach 2:
The patent implements parameter changes by modifying delay values and timing parameters based on detected timing skews and operating conditions. The system changes delay parameters dynamically in response to PVT variations, adjusting signal timing to compensate for changes in process, voltage, and temperature. This adaptive parameter adjustment maintains write operation stability and calibration accuracy under varying conditions.
3Reliability
If signal timing is adjusted for different memory modules, then timing skew is compensated, but device complexity increases due to multiple delay values
Solution Approach 1:
The patent applies universality by implementing a single memory controller that handles multiple types of memory modules (e.g., DDR3 DIMM, RDIMM, UDIMM) with different timing requirements. The controller uses a unified approach to timing adjustment, employing delay value tables and dynamic adjustment mechanisms that work across all memory module types. This multi-functional design allows the same controller to compensate for timing skews in various memory configurations without requiring separate specialized controllers for each module type, thereby managing complexity while maintaining reliability.
Data Source
AI summary
A write leveling control method which includes registering data-related signal (DRS) reference delay values corresponding to types of memory modules in a leveling reference table; transmitting write leveling-related signals to a first type of memory module mounted on a target board; detecting timing skews between a clock signal and data-related signals received from memory devices on the mounted memory module; and adjusting a delay of a data-related signal transmitted to a memory device of the mounted memory module if a corresponding timing skew is outside of a first range, based on the DRS reference delay value corresponding to the mounted memory module.