Write Memory Bandwidth Tracking via Cache Line Dirty Monitoring
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Solution Overview
Problem
Existing methods fail to efficiently measure write memory bandwidth in computing systems due to challenges in tracking cache line modifications and thread class information, especially in cache hierarchies where write operations can result from cache evictions and lack of class indication.
Innovation Solution
Implementing a system with a control unit that monitors cache line writes, increments counters for first-time modifications, and maintains separate counters for different thread classes to calculate write memory bandwidth, allowing for efficient measurement and bandwidth management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If thread class information is stored in each cache line, then quality of service tracking is enabled, but cache area consumption increases significantly
Solution Approach 1:
The patent extracts the thread class information from the cache line metadata and stores it separately in a thread class table indexed by virtual address. This allows QoS tracking without consuming cache line area, resolving the contradiction between measurement precision and cache area consumption
Solution Approach 2:
The patent introduces a thread class table as an intermediary data structure that maps virtual addresses to thread class identifiers. This mediator enables QoS tracking while keeping the cache line structure unchanged and area-efficient
2Measurement precision
If thread class information is stored in cache lines, then per-thread-class bandwidth measurement is possible, but the information becomes stale when software changes thread classes
Solution Approach 1:
The patent implements feedback by having the thread class table updated whenever software changes thread classes. The control unit continuously monitors and updates the thread class information, ensuring the measurement data remains current and reliable without requiring changes to cache line structures
Solution Approach 2:
The patent performs preliminary action by maintaining and updating the thread class table in advance of any cache operations. This ensures that when bandwidth measurement is needed, the thread class information is already current and accurate, preventing staleness
3Measurement precision
If all writes to cache lines are counted, then write memory bandwidth is overestimated, but tracking first-time modifications only misses subsequent modifications
Solution Approach 1:
The patent applies local quality by making different parts of the measurement process serve different purposes: the dirty bit tracks local cache line modification state, while the control unit logic distinguishes between first-time and subsequent writes. This allows precise measurement of only relevant writes (first-time modifications) without counting redundant operations
Data Source
AI summary
Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.