Write-Once Memory Diagonal Bit Cell Testing
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Solution Overview
Problem
Conventional write-once memory (WOM) devices require burning entire rows and columns of bit cells to test peripheral circuits, leading to unnecessary waste of usable memory cells due to their non-reversible nature.
Innovation Solution
A novel WOM device incorporates a control logic circuit that uses diagonal bit cells to test row and column decoders, minimizing the number of bit cells that become unusable by selectively burning only those along the diagonal for testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional WOM devices burn entire rows and columns of memory cells to test peripheral circuits, then the testing completeness of peripheral circuits is improved, but the waste of usable memory cells increases
Solution Approach 1:
The patent segments the testing process by dividing the memory array into distinct row testing and column testing phases. During row testing, only the specific row being tested is activated and burned, rather than the entire memory array. Similarly, during column testing, only the specific column is activated. This segmentation allows comprehensive peripheral circuit testing while minimizing the number of memory cells that become unusable.
Solution Approach 2:
The patent applies partial action by testing and burning only the necessary portions of the memory array required to validate peripheral circuit functionality. Instead of burning entire rows and columns which would excessively waste memory cells, the method selectively activates and tests specific address lines and their corresponding minimal set of memory cells, achieving sufficient testing coverage with minimal loss.
2Reliability
If WOM devices use dummy memory cells for testing, then the reliability of original memory cells is improved, but the device complexity increases
Solution Approach 1:
The patent makes the memory cells universal by enabling them to serve dual purposes: as functional storage cells during normal operation and as test subjects during manufacturing testing. The same memory cells that store data are also used to test the peripheral circuits, eliminating the need for separate dummy test cells. This multi-functionality reduces device complexity while maintaining testing capability.
Solution Approach 2:
The memory array itself performs the testing function by using its own cells to validate the peripheral circuits. The system is self-sufficient and does not require external or additional dedicated test structures. The memory cells test the address decoders and other peripheral components through controlled activation and burning, making the testing process self-contained.
Data Source
AI summary
A memory device, includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing one or more peripheral circuits coupled to the memory array, wherein the control logic circuit is further configured to determine respective locations of at least a second plurality of diagonal bit cells of the memory array for testing the one or more peripheral circuits, wherein a number of the plurality of rows is different than a number of the plurality of columns and the first plurality of diagonal bit cells span a first equal number of rows and columns and the second plurality of diagonal bit cells also span a second equal number of rows and columns.