Write-Once Memory Encoding for Flash Endurance

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Solution Overview

Problem

Memory devices, such as NAND flash memory, face challenges in extending their lifespan due to increased bit-error rates (BER) resulting from repeated program/erase cycles, which lead to reduced endurance and increased total number of erases between programming operations.

Innovation Solution

The implementation of Write-Once Memory (WOM) encoded data within memory sub-systems, which allows for multiple programming operations without performing an erase operation between them, thereby reducing the total number of erases and extending the memory device's lifespan.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If repeated program/erase cycles are performed to increase storage capacity utilization, then more data can be stored and retrieved, but the bit-error rate increases and endurance decreases

Engineering Contradiction:
Improvestorage capacity utilizationVSAvoidbit-error rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory system segments data storage into multiple pages within a block. By allowing multiple programming operations on different pages without intermediate erases, the system increases storage utilization while maintaining reliability. The block is divided into pages that can be independently programmed, enabling efficient use of storage capacity without subjecting the entire block to repeated erase cycles.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs a preliminary erase operation on the entire block before initiating multiple programming operations on individual pages. This preliminary action resets the block to a known state, allowing subsequent pages to be programmed without requiring intermediate erases. The counter mechanism tracks programming operations to determine when the next erase should occur, optimizing the balance between storage utilization and reliability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If erase operations are performed frequently to maintain data integrity, then bit-error rate is reduced, but the total number of bits written (TBW) decreases and lifespan is reduced

Engineering Contradiction:
Improvedata integrityVSAvoidmemory device lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The system enables continuous programming operations across multiple pages within a block without interrupting for intermediate erases. The counter tracks the number of programming operations and only triggers an erase when the threshold is reached, allowing the memory device to maintain data integrity through controlled erasing while maximizing the total number of bits written over its lifespan.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

A counter mechanism provides feedback on the number of programming operations performed on each block. This feedback controls when erase operations should be performed, ensuring that erases occur only when necessary to maintain data integrity. The system monitors and regulates erase frequency based on actual usage patterns, preventing premature erases that would reduce device lifespan.

Inventive Principle:
Principle #23Feedback

3Duration of action of stationary object

If the number of erases between programming operations is increased to extend lifespan, then device longevity improves, but storage capacity utilization and productivity decrease

Engineering Contradiction:
Improvedevice longevityVSAvoidstorage capacity utilization
Core Design Contradiction:
Duration of action of stationary objectVSProductivity

Solution Approach 1:

By segmenting the block into multiple programmable pages, the system allows intensive use of storage capacity through multiple programming operations on different pages before a single erase is required. This segmentation enables high storage utilization while limiting the total number of erases per block, thereby extending device longevity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the parameter of erase frequency by introducing a counter that tracks programming operations. Instead of erasing after each program operation or after a fixed time period, the system adjusts erase timing based on the number of programming operations performed, optimizing the balance between storage utilization and device lifespan.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12334154B2Write-once memory encoded data
Publication Date: 2025.06.17 MICRON TECHNOLOGY INC
  • US12334154B2 patent drawing
  • US12334154B2 patent drawing
  • US12334154B2 patent drawing

AI summary

A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.