ECC Circuit Write-Phase Parity Precompute for Read Timing Margin
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Solution Overview
Problem
As semiconductor apparatuses, such as memory devices, operate at increasingly higher speeds, the bit error rate increases, necessitating more effective error correction mechanisms to maintain reliability.
Innovation Solution
The proposed error correction code circuit includes an ECC engine and a data processing circuit that generate a second parity signal and syndrome information by performing ECC operations on operation source data and a first parity signal. During write operations, a dummy parity signal is used as the first parity signal, while during read operations, a read parity signal is used. This configuration improves ECC operation timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating speed is increased, then productivity is improved, but bit error rate increases
Solution Approach 1:
The patent applies preliminary action by generating the second parity signal in advance during write operations using a dummy first parity signal. This pre-computed second parity signal is stored alongside the data, enabling faster error correction during read operations without adding to the critical read path latency, thus maintaining high operating speed while ensuring data reliability through pre-prepared error correction capability.
2Reliability
If ECC operation timing margin is improved, then reliability is improved, but operation time increases
Solution Approach 1:
The patent performs the computationally intensive second parity signal generation during write operations when time is abundant, storing the result for later use. During read operations, the pre-computed second parity signal is immediately available, providing ample timing margin for reliable ECC operation without extending the critical read path duration, thus resolving the contradiction between reliability and operation time.
Solution Approach 2:
The patent dynamically adapts the first parity signal input based on operation type: using a dummy signal during writes when computation time is available, and using actual read parity signals during reads when timing is critical. This dynamic adaptation optimizes the balance between timing margin and operation time for different operational contexts.
Data Source
AI summary
In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.