Write Signal Interference Cancellation Across Clock Boundary

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Solution Overview

Problem

Existing disk drive technologies face inefficiencies due to the need to stop write operations during servo read operations to prevent interference, resulting in wasted disk medium space.

Innovation Solution

A method and controller architecture that generate a predicted channel response signal from write signals in the data clock domain, resample it to match the servo clock domain, align its phase with the servo clock, and subtract it from servo signals to cancel interference, allowing continuous writing during servo read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If write operations are stopped during servo read operations to prevent interference, then servo read accuracy is improved, but disk medium space utilization deteriorates

Engineering Contradiction:

Improveservo read accuracyVSAvoiddisk medium space utilization

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent converts the harmful write signal interference into a beneficial cancellation mechanism by generating a predicted channel response signal from the write signals and subtracting it from the servo read signals. This allows write operations to continue during servo reads while eliminating the interference through signal processing.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces an intermediary predicted channel response signal that mediates between the write signals and servo read signals. This intermediate signal is generated based on write signal characteristics and used to cancel the interference, enabling both write and read operations to proceed simultaneously.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If write operations continue during servo read operations, then disk medium space utilization is improved, but servo read accuracy deteriorates due to write signal interference

Engineering Contradiction:

Improvedisk medium space utilizationVSAvoidservo read accuracy

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent applies preliminary anti-action by generating the predicted channel response signal in advance based on the write signals, before the interference affects the servo read operation. This pre-computed cancellation signal is then subtracted from the servo read signal to prevent interference degradation.

Inventive Principle:

Principle #9Preliminary anti-action

3Adaptability or versatility

If different clock domains are used for data and servo operations, then operational flexibility is improved, but signal synchronization deteriorates

Engineering Contradiction:

Improveoperational flexibilityVSAvoidsignal synchronization

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary resampling process that mediates between the data clock domain and servo clock domain. The predicted channel response signal is resampled from the data clock rate to the servo clock rate, enabling synchronization while maintaining the benefits of separate clock domains for data and servo operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12243557B1Write signal interference cancellation across data/servo clock boundary

Publication Date: 2025.03.04 MARVELL ASIA PTE LTD

AI summary

A method for cancelling, from servo signals read in a read channel while a write channel is active, interference caused by write signals in the write channel, includes generating a predicted channel response signal from the write signals in a data clock domain, resampling the generated predicted channel response signal using a clock in the data clock domain having a rate corresponding to a servo clock from a servo clock domain, transferring the resampled predicted channel response signal from the data clock domain to the servo clock domain and aligning phase of the transferred resampled predicted channel response signal with phase of the servo clock, determining a domain-boundary-crossing delay incurred in the transferring, based on the domain-boundary-crossing delay, synchronizing the phase-aligned transferred resampled predicted channel response signal with the servo signals, and subtracting the synchronized phase-aligned transferred resampled predicted channel response signal from the servo signals.