Write Suppression in Non-Volatile Memory via Tiered Storage
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Solution Overview
Problem
Quad-level cell (QLC) NAND flash memories face significant challenges due to lower endurance and longer read times as a result of increased precision in adjusting threshold voltage levels, leading to reduced durability and performance, necessitating effective write suppression techniques to extend their lifespan.
Innovation Solution
Implementing a fast-slow memory concatenation scheme where data is initially written to a high-endurance fast memory and then selectively transferred to a lower-endurance slow memory based on validity and age, using a frontend manager to optimize write suppression, allowing for 3× or higher write suppression on typical workloads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple level programming is used to store more information per cell, then storage capacity increases, but endurance decreases and read times increase
Solution Approach 1:
The patent divides the non-volatile memory into multiple tiers with different characteristics (fast/high-endurance and slow/low-endurance memory). Data is segmented and distributed across these tiers based on access patterns and validity, allowing the system to achieve high storage capacity while protecting endurance by limiting write operations on the low-endurance memory portion.
2Quantity of substance
If multiple level programming is used to store more information per cell, then storage capacity increases, but read times increase
Solution Approach 1:
The patent applies local quality by assigning different performance characteristics to different portions of the memory system. The fast memory portion is optimized for quick reads of frequently accessed valid data, while the slow memory portion provides additional storage capacity for less frequently accessed data. This allows the system to achieve high overall storage capacity while maintaining fast read times for active data.
Solution Approach 2:
The system performs preliminary actions by pre-transferring data from slow memory to fast memory before it is needed, based on predicted access patterns. This preliminary positioning of data in the fast memory portion ensures that when reads occur, the data is already in the optimal location, reducing actual read times while maintaining high storage capacity.
3Reliability
If write suppression is implemented to extend lifespan, then endurance increases, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary component (the controller with write suppression logic) that manages data flow between the host and the multi-tier memory system. This intermediary tracks data validity and age, making intelligent decisions about where to write data and when to transfer it between tiers. While this adds some complexity, it significantly extends endurance by preventing unnecessary writes to the low-endurance memory, justifying the added complexity through substantial reliability improvement.
Data Source
AI summary
Techniques are disclosed for write suppression to improve endurance rating of non-volatile memories, such as QLC-NAND SSDs or other relatively slow, low endurance non-volatile memories. In an embodiment, an SSD is configured with a fast frontend non-volatile memory, a relatively slow lower endurance backend non-volatile memory, and a frontend manager that selectively transfers data from the fast memory to the slow memory based on transfer criteria. In operation, write data from the host is initially written to the fast memory by the frontend manager. The data is moved from the fast memory to the slow memory in bands. For each data band stored in the fast memory, the frontend manager tracks invalid data counts and data age. Only bands that still remain valid are transferred to the slow memory. After a given band has been fully transferred, it is erased and re-usable for other incoming writes by the frontend manager.