Self-Timed Memory Write Timer Cells Voltage Adaptation
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Solution Overview
Problem
Self-timed memory circuits face challenges in maintaining optimal write cycle time across a wide range of supply voltages, with existing solutions leading to sub-optimal performance at higher voltages and abrupt changes in write cycle performance when voltage transitions occur.
Innovation Solution
The introduction of a circuit that generates an intermediate supply voltage higher than the logic low voltage by an amount equal to the expected shift in threshold voltage of the pullup devices in memory cells with statistically worst write times, and the use of write timer cells with reduced gate-to-source voltage of pullup transistors to match the overdrive factor of memory cells, ensuring consistent write cycle time across voltage ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If write timer cells use standard gate-to-source voltage for pullup transistors, then they operate correctly at nominal voltage, but write cycle time becomes sub-optimal at higher operating voltages
Solution Approach 1:
The patent applies dynamics by making the gate-to-source voltage of pullup transistors in write timer cells variable rather than fixed. The voltage is dynamically adjusted based on the operating voltage level, allowing the write timer cells to maintain optimal performance across the entire voltage range from low to nominal operating voltages.
Solution Approach 2:
The patent changes the parameter of gate-to-source voltage for pullup transistors in write timer cells according to operating conditions. By modifying this electrical parameter dynamically, the write timer cells adapt their behavior to match the overdrive factor of memory cells at different voltage levels, ensuring consistent write cycle time.
2Productivity
If write timer cells operate at nominal voltage, then high-frequency performance is achieved, but functionality is lost at lower operating voltages
Solution Approach 1:
The patent makes the operating characteristics of write timer cells dynamic by adjusting gate-to-source voltage based on supply voltage levels. This allows the cells to maintain functionality across the full voltage range while preserving high-frequency performance at nominal voltages.
Solution Approach 2:
The patent modifies electrical parameters (gate-to-source voltage) of pullup transistors in response to operating conditions. This parameter adjustment ensures that write timer cells remain functional and perform optimally whether operating at low or nominal voltages.
3Speed
If write cycle time is optimized for nominal voltage, then high performance is achieved, but abrupt performance changes occur during voltage transitions
Solution Approach 1:
The patent implements dynamic adjustment of gate-to-source voltage for pullup transistors in write timer cells based on operating voltage. This dynamic behavior smooths performance transitions during voltage changes, eliminating abrupt performance variations and maintaining stable write cycle time across voltage transitions.
Solution Approach 2:
The patent changes the gate-to-source voltage parameter dynamically during voltage transitions. By continuously adjusting this parameter, the write timer cells maintain consistent operation throughout voltage changes, preventing abrupt performance shifts and ensuring stable write cycle time.
Data Source
AI summary
A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.