Write Word-Line Assist Circuitry for 8T SRAM
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Solution Overview
Problem
The use of eight-transistor (8T) SRAM cells in semiconductor memory devices faces challenges due to weak bits caused by nanometer technology process variations, which limit the minimum write voltage (Vmin) and read/write margins, especially in large size SRAM cache memory arrays, and conventional write word-line assist circuitry incurs area and power costs.
Innovation Solution
Implementing a write word-line assist circuitry where a main write word-line decoder operates in a low VDD power domain and a local write word-line decoder operates in a high VDD power domain, generating global and local write word-line signals to enable write assistance in byte-writeable memory, allowing independent sizing of read and write ports and improving write margin and read current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 8T SRAM cells are used to enable independent sizing of read and write ports, then write voltage requirement is reduced, but weak bits caused by process variations still limit read/write margins
Solution Approach 1:
The write word-line decoder is segmented into two separate decoders: a global write word-line decoder receiving bank select and word line select signals, and a local write word-line decoder receiving the global write word-line signal and write byte select signal. This segmentation allows independent optimization of each decoder's functionality and sizing, improving write margin while managing complexity.
Solution Approach 2:
The global write word-line signal serves as an intermediary between the global decoder and local decoder stages. This intermediate signal enables cascaded decoding architecture where the global signal activates the local decoder, which then generates the final write word-line signal with enhanced margin.
2Reliability
If write word-line assist circuitry is implemented to improve write margin, then write reliability is enhanced, but area and power consumption increase
Solution Approach 1:
The local write word-line decoder is implemented in a high VDD power domain while the global decoder operates in a low VDD power domain. This dynamic voltage domain separation allows the assist circuitry to activate only when high write margin is needed, reducing average power consumption and area utilization compared to a always-active high-voltage decoder.
Solution Approach 2:
Different parts of the decoder system operate at different voltage domains: the global decoder operates at low VDD while the local assist decoder operates at high VDD. This local quality differentiation ensures that high voltage (and thus high power) is applied only where and when needed for write assistance, minimizing overall area and power overhead.
3Reliability
If local write word-line decoder operates in high VDD domain to improve write assist, then write margin is enhanced, but power consumption increases
Solution Approach 1:
The system dynamically switches between low VDD and high VDD power domains based on operational requirements. The local write word-line decoder operates in high VDD domain only when write assistance is needed, while the global decoder operates continuously in low VDD domain, optimizing the balance between write margin and power consumption.
Solution Approach 2:
The voltage parameter VDD is changed based on operational mode: low VDD for global decoder operation and high VDD for local assist decoder operation. This parameter change allows the system to achieve high write margin only when necessary, reducing average power consumption compared to maintaining high VDD throughout.
Data Source
AI summary
A write-assisted memory. The write-assisted memory includes a word-line decoder that is implemented within a low VDD power domain. The write-assisted memory also includes a write-segment controller that is partially implemented within the low VDD power domain and is partially implemented within a high VDD power domain. The write-assisted memory further includes a local write word-line decoder that is implemented within the high VDD power domain.