Write-back Cache Device with Unit Data Dirty Bits
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Solution Overview
Problem
Current write-back cache systems using non-volatile memory like MRAM face inefficiencies due to high write frequency and data volume, as they write entire cache lines when only one piece of data is dirty, leading to increased current consumption and latency.
Innovation Solution
A write-back cache device configuration that allows multiple unit data pieces per cache line, using state instruction data with fewer bits to differentiate clean and dirty states, reducing the amount of data written to the main memory by only writing dirty data, thereby minimizing circuit dimensions and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one dirty bit is allocated to one cache line to manage write status, then the management of dirty data is simplified, but all pieces of unit data in the cache line are written to the main memory even if only one piece is dirty, resulting in an increase in the amount of data to be written
Solution Approach 1:
The cache line is segmented into multiple unit data pieces, each with its own dirty bit. This allows individual tracking of dirty status for each unit data piece rather than treating the entire cache line as a single unit. When only one piece is dirty, only that specific piece is written to main memory, reducing the total amount of data written while maintaining simplified management through systematic bit tracking.
Solution Approach 2:
Each unit data piece within the cache line is assigned a distinct dirty bit, creating local quality differentiation. This enables precise control over which specific data pieces need to be written back, allowing the system to write only the necessary portions rather than entire cache lines, thereby optimizing write efficiency.
2Ease of operation
If all pieces of unit data in a cache line are written to the main memory when the dirty bit is dirty, then the write-back operation is simplified, but the current consumption and latency increase
Solution Approach 1:
Instead of writing all unit data pieces in a cache line when any are dirty, the system performs partial action by writing only the specific dirty pieces identified by their individual dirty bits. This reduces unnecessary write operations, lowering current consumption and latency while maintaining the simplicity of the write-back mechanism through systematic dirty bit checking.
Solution Approach 2:
The system changes the parameter of dirty bit allocation from one bit per cache line to one bit per unit data piece. This parameter change enables selective writing based on actual dirty status, reducing the number of write operations and their associated energy consumption while preserving operational simplicity through structured bit management.
3Device complexity
If all pieces of unit data in a cache line are written to the main memory when the dirty bit is dirty, then the write-back logic is simplified, but the latency at writing increases
Solution Approach 1:
The cache line is divided into multiple unit data pieces with individual dirty bits, enabling selective write-back of only the dirty pieces. This segmentation reduces the total number of write operations required, thereby reducing the time lost to write operations while maintaining logical simplicity through systematic dirty bit checking and targeted writing.
Solution Approach 2:
The system performs partial write actions by writing only the dirty unit data pieces rather than entire cache lines. This reduces the total write volume and associated latency, while the write-back logic remains simple through the use of individual dirty bits to identify which pieces require writing.
Data Source
AI summary
A write-back cache device of an embodiment includes a first storage device capable of storing n pieces of unit data in each of a plurality of cache lines, a second storage device configured to store state instruction data in each of the plurality of cache lines, and a cache controller configured to control inputting to and outputting from the first and second storage devices. The state instruction data has a first value when data in a cache line is not different from data in a main memory, has a second value when two or more pieces of unit data are different from data in the main memory, or has a third value when only one piece of unit data is different from data in the main memory.