Parallelism-Aware WRONoC Design Flow for Optical Networks
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Solution Overview
Problem
As the number of cores in a wavelength-routed optical network-on-chip (WRONoC) increases, some topologies become infeasible due to bandwidth and crosstalk constraints, especially when bit-level parallelism is not considered during topology generation, leading to suboptimal results.
Innovation Solution
A parallelism-aware WRONoC design flow that optimizes topology generation and MRR radius selection using simulated annealing, ensuring full connectivity and customized connectivity by determining potential positions of cores, waveguides, and microring resonators, and minimizing MRR type usage through ILP formulations and routing mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cores in WRONoC increases, then the communication capacity and parallelism processing capability improve, but the topology becomes infeasible due to bandwidth and crosstalk constraints
Solution Approach 1:
The patent applies preliminary action by considering bit-level parallelism during the topology generation phase itself, rather than after. The design flow pre-determines waveguide paths and MRR configurations that guarantee feasible bandwidth and crosstalk constraints are met from the outset, enabling larger core counts while maintaining topology feasibility.
Solution Approach 2:
The patent changes the parameter of topology generation by introducing bit-level parallelism consideration. Instead of generating topologies at the traditional packet-level, the method generates topologies that support multiple wavelengths simultaneously, effectively changing the granularity and parameters of network construction to accommodate higher core counts.
2Productivity
If traditional topology generation methods are used, then the design process is simple, but the achieved parallelism is suboptimal
Solution Approach 1:
The patent segments the topology generation process into distinct phases: network construction, message routing, and MRR radius selection. Each phase handles specific aspects of the design, making the overall complex optimization manageable through systematic decomposition while achieving optimal parallelism.
Solution Approach 2:
The patent implements feedback mechanisms where the design flow iterates and refines topology configurations based on parallelism evaluation. The system evaluates generated topologies and adjusts waveguide paths, MRR types, and radii to maximize parallelism, creating a feedback-driven optimization process.
3Adaptability or versatility
If more MRR types are used to support full connectivity, then the network adaptability improves, but the device complexity and resource consumption increase
Solution Approach 1:
The patent applies universality by designing a topology that can support multiple connectivity patterns and communication scenarios using a unified structure. The generated topology provides full connectivity capability while using a minimized set of MRR types, making the design adaptable to various communication needs without proportionally increasing complexity.
Solution Approach 2:
The patent applies local quality by assigning different MRR types to different locations and functions within the network topology. Instead of uniformly using all MRR types everywhere, the design selectively assigns types based on local connectivity requirements, optimizing both adaptability and complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design achieves a 42.2% improvement in parallelism and significantly reduces runtime without performance loss, enabling the generation of parallelism-optimal topologies for larger network sizes compared to existing methods.
Implementation Method 1
The wavelength-routed optical network-on-chip (WRONoC) uses passive MRRs, which set up signal paths during design time
Data Source
AI summary
A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.