X-Behavior Verification in Electronic Design via Hierarchical Decomposition
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Solution Overview
Problem
Conventional approaches for X-propagation verification in electronic design automation (EDA) tools face challenges in handling complex designs with complex logic elements, lacking effective methods for hierarchical decomposition and unified specifications for different types of nets, which complicates the capture and verification of X-behavior.
Innovation Solution
A method and system for verifying X-behavior in electronic designs by identifying input, output, and internal nodes, extracting preconditions and harmless conditions, and performing hierarchical verification decomposition to generate internal proof results, allowing for unified specification and manipulation of X-propagation verification across various net types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional approaches are used for X-propagation verification, then verification can be performed for simple designs, but the approach fails to handle complex designs with complex logic elements and lacks effective hierarchical decomposition
Solution Approach 1:
The verification task is divided into hierarchical levels (top-level design and sub-module levels). Each level has its own verification specifications and proof obligations. This segmentation allows complex verification tasks to be broken down into manageable sub-tasks that can be handled independently at each hierarchical level, resolving the contradiction between handling complex designs and managing verification complexity.
Solution Approach 2:
The patent introduces a hierarchical dimension to the verification process. Instead of treating all verification at a single level, the system operates across multiple hierarchical levels, allowing complex logic elements to be verified at appropriate levels of abstraction. This dimensional approach enables the system to handle complexity by distributing verification across different levels rather than concentrating it all at once.
2Reliability
If different specifications are used for different types of nets, then each net type can be verified appropriately, but the verification process becomes complicated and lacks a unified approach
Solution Approach 1:
The patent creates a unified specification framework that can handle different types of nets (combinational, sequential, mixed) through a common interface. The hierarchical specification system and proof obligation generation mechanism work universally across all net types, eliminating the need for separate verification processes for each net type while maintaining accuracy through level-specific refinement.
Solution Approach 2:
While maintaining a unified hierarchical specification framework, the patent allows each level and module to have locally optimized specifications tailored to its specific characteristics. This means that although the overall approach is unified, each local context (module level, net type, logic element) can have appropriate verification details, achieving both unity and local optimization.
3Adaptability or versatility
If hierarchical decomposition is not used, then the verification task remains simple to manage, but complex designs cannot be effectively verified
Solution Approach 1:
The verification task is divided into hierarchical levels (top-level design and sub-module levels). Each level has its own verification specifications and proof obligations. This segmentation allows complex verification tasks to be broken down into manageable sub-tasks that can be handled independently at each hierarchical level, resolving the contradiction between handling complex designs and managing verification complexity.
Solution Approach 2:
The patent introduces intermediate specification layers at each hierarchical level that act as mediators between the top-level requirements and the detailed module-level implementations. These intermediate specifications serve as contracts that bridge different levels of the hierarchy, enabling verification of complex designs while keeping each level's complexity manageable through well-defined interfaces.
Data Source
AI summary
Disclosed are techniques for verifying X-behavior in electronic designs. These techniques identify at least a portion of an electronic design, wherein the at least the portion that includes an input node, an output node, and an internal node located between the input node and the output node. Internal X-propagation proof results may be generated for the internal node based in part or in whole upon an internal precondition and an internal harmless condition for the internal node. X-propagation verification for the output node may then be performed based in part upon one or more assumed properties at the internal node, wherein the one or more assumed properties are assumed at the internal node based in part or in whole upon the internal X-propagation proof results.