Local X-Decoder Voltage Clamping for Gate Oxide Reliability

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Solution Overview

Problem

In NOR flash memory systems, the local X-decoder experiences reliability issues due to high voltage differences across the gate oxide, leading to well disturb failures and gate-induced drain leakage, which can damage the decoder over time.

Innovation Solution

A local X-decoder design incorporating a voltage clamping transistor that reduces the voltage difference across the global word line signal and the word line signal by the threshold voltage of the transistor, thereby mitigating these issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the local X-decoder uses a conventional design without voltage clamping, then the decoder structure is simple, but the voltage difference across the gate oxide becomes too high causing well disturb failures and gate induced drain leakage

Engineering Contradiction:
Improvedecoder reliabilityVSAvoiddecoder structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a voltage clamping transistor as an intermediary component between the global word line signal and the local word line signal. This transistor acts as a mediator that limits the voltage difference across the gate oxide by clamping it to a safe level, thereby preventing well disturb failures and gate induced drain leakage without fundamentally redesigning the entire decoder structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the voltage parameter by introducing a voltage clamping mechanism that limits the maximum voltage difference across the gate oxide. The voltage clamping transistor modifies the voltage waveform by clamping the voltage difference to a safe level (below the breakdown voltage), thereby improving reliability without requiring a complete structural overhaul

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the voltage difference across the gate oxide is reduced using a voltage clamping transistor, then well disturb failures and gate induced drain leakage are prevented, but the decoder structure becomes more complex

Engineering Contradiction:
Improvedecoder reliabilityVSAvoiddecoder structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The voltage clamping transistor serves as an intermediary element that is strategically placed in the circuit to limit voltage stress. This single component acts as a protective mediator that prevents harmful voltage differences from reaching the gate oxide, improving reliability with minimal structural modification

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The voltage clamping transistor provides beforehand cushioning by preemptively limiting the voltage difference across the gate oxide before it can reach dangerous levels. This protective mechanism is in place before well disturb failures or gate induced drain leakage can occur, preventing damage in advance

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the voltage difference across the gate oxide, preventing well disturb failures and gate-induced drain leakage, enhancing the reliability of the local X-decoder and extending its operational lifespan.

Implementation Method 1

configured to reduce a voltage difference across a global word line signal and the word line signal by an amount of a threshold voltage of the voltage clamping transistor

Methodology Applied
Scientific EffectThreshold voltage effect:

Data Source

PatentUS10748618B2Local X-decoder and related memory system with a voltage clamping transistor
Publication Date: 2020.08.18 WUHAN XINXIN SEMICON MFG CO LTD
  • US10748618B2 patent drawing
  • US10748618B2 patent drawing
  • US10748618B2 patent drawing

AI summary

A local X-decoder for a memory system including a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and a voltage clamping transistor coupled to the decoding unit, and configured to reduce a voltage difference across a global word line signal and the word line signal by an amount of a threshold voltage of the voltage clamping transistor.