X-Line Routing for Dense Multi-Chip Package Interconnects
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high-density interconnects with minimal capacitance and crosstalk, particularly in multi-chip packages, due to limitations in signal routing designs such as microstrip and stripline approaches which can lead to signaling bottlenecks and degraded performance.
Innovation Solution
The implementation of X-line routing, which increases the distance between signal lines and ground traces, creating voids in the ground layers to minimize parallel plate capacitance and offset signals in adjacent layers to avoid crosstalk, while maintaining suitable metal density for manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional microstrip or stripline routing is used in multi-chip packages, then routing implementation is simplified, but capacitance increases and crosstalk occurs leading to degraded signaling performance
Solution Approach 1:
The ground layers are segmented to create voids directly above and underneath signal lines. This segmentation removes harmful ground plane areas that cause parallel plate capacitance, while retaining ground planes in regions that provide crosstalk suppression. The selective removal and retention of ground plane segments resolves the contradiction by eliminating capacitance sources without sacrificing shielding benefits.
Solution Approach 2:
Different regions of the ground layers are assigned different functions: areas directly above and underneath signal lines are removed to minimize capacitance, while other areas retain ground planes for crosstalk suppression. This local differentiation of ground plane presence creates optimal electrical characteristics at each location, improving overall signaling performance while maintaining manufacturability.
2Reliability
If ground planes are removed to minimize parallel plate capacitance, then capacitance decreases, but crosstalk suppression capability is reduced
Solution Approach 1:
Ground planes are segmented rather than completely removed. Voids are created only in specific regions directly above and underneath signal lines where parallel plate capacitance is problematic, while ground planes are retained in adjacent regions to provide electromagnetic shielding and suppress crosstalk between adjacent signal traces.
Solution Approach 2:
The ground layer structure is optimized with local quality variations: absence of ground planes in capacitance-critical areas and presence of ground planes in crosstalk-critical areas. This spatially differentiated approach simultaneously minimizes parallel plate capacitance and maintains crosstalk suppression capability.
3Productivity
If signal lines are closely routed to increase interconnect density, then packaging density increases, but capacitance and crosstalk increase degrading performance
Solution Approach 1:
Harmful ground plane areas that cause parallel plate capacitance are extracted or removed from the structure. By taking out the ground planes directly above and underneath signal lines, the patent enables closely routed signal lines to achieve high interconnect density without suffering from excessive capacitance that would normally limit density.
Solution Approach 2:
The ground layer configuration is locally optimized to support high-density routing: voids are created in regions that would otherwise create capacitance with closely spaced signal lines, while ground planes are retained in regions that provide inter-signal crosstalk suppression. This enables high density while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
X-line routing effectively reduces capacitance, improves signal resistance, and suppresses crosstalk, leading to enhanced signaling performance and increased bandwidth in dense multi-chip-package interconnects, overcoming the limitations of existing routing designs.
Implementation Method 1
increases the distance between signal lines and ground traces, creating voids in the ground layers to minimize parallel plate capacitance
Implementation Method 2
offset signals in adjacent layers to avoid crosstalk
Data Source
AI summary
X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.