Metastability Insertion Using X-State in RTL Simulation
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Solution Overview
Problem
Current methods for simulating metastable events in digital designs are computationally intensive and slow, limiting their ability to accurately assess the impact of such events early in the design cycle, and often fail to visualize the non-deterministic behavior caused by glitches, asynchronous resets, and clock domain crossing violations.
Innovation Solution
The Metastability Insertion through X-state (MIX) technique introduces a non-deterministic X-state into circuit outputs during RTL simulation, maintaining it for a specified time and then randomly resolving it, allowing designers to visualize and address metastable issues more effectively, and can be implemented in various hardware verification languages and environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard delay format (SDF) back annotated gate simulations with timing checks are used to evaluate metastability, then measurement precision is improved, but productivity deteriorates due to computational intensity and slow simulation speed
Solution Approach 1:
The patent uses lightweight, simplified circuit models instead of full physical design models for metastability simulation. These simplified models are computationally inexpensive and can be executed quickly during RTL simulation, sacrificing some physical accuracy for dramatically improved simulation speed and early design cycle usability.
2Measurement precision
If physical design-based simulation is used for metastability analysis, then measurement precision is improved, but loss of time increases because it can only be run during end phases of design cycle
Solution Approach 1:
The patent enables metastability simulation to be performed at the RTL design phase, which is preliminary to physical design. By using simplified circuit models that do not require physical design artifacts, the simulation can be conducted early in the design cycle, allowing designers to identify and fix metastability issues before committing to physical implementation.
3Productivity
If simplified models are used for early design cycle simulation, then productivity is improved, but measurement precision deteriorates
Solution Approach 1:
The patent applies simplified circuit models specifically to metastability evaluation while maintaining other aspects of design simulation fidelity. The simplification is localized to the metastability analysis function, allowing efficient simulation without compromising overall design accuracy for other purposes.
Data Source
AI summary
An indeterminate state representative of a metastable state is inserted into an output signal of a circuit representation responsive to the circuit representation receiving a metastable triggering event during a register transfer language (RTL) simulation. The simulation view of the RTL has been modified to ensure that the indeterminate state is propagated through the circuit representations regardless of the input on which the indeterminate state appears. The indeterminate state is maintained for a programmable amount of time and responsive to expiration of the amount of time, the output signal is set to a random binary value.