Frequency Scaling for X25519 Modular Multiplication
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Solution Overview
Problem
Current encryption techniques, such as x25519 algorithms, are computationally expensive and require significant resources, leading to performance issues in devices like smartphones that need to securely transmit data over networks, especially when they have limited power and general-purpose hardware not optimized for encryption.
Innovation Solution
The implementation of frequency scaler circuitry that selects a subset of processor cores to perform computationally expensive tasks like encryption, increasing the operating frequency of these cores while decreasing the frequency of others to conserve power and reduce computational time, and performing x25519 modular multiplication in the 25638 (25519<<1) domain to reduce clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If x25519 encryption algorithms are used to provide security, then security is improved, but computational resources and time are significantly consumed
Solution Approach 1:
The patent segments the processor into multiple cores, with specific cores dedicated to performing encryption operations. This segmentation allows the system to allocate computational resources more efficiently, dedicating only the necessary processing power to encryption tasks while leaving other cores available for general-purpose operations, thereby improving overall computational efficiency without compromising security.
Solution Approach 2:
The patent implements dynamic frequency scaling where the operating frequency of processor cores is adjusted based on whether they are performing encryption tasks. Cores engaged in encryption operations are assigned higher frequencies to accelerate computation, while non-encryption cores operate at lower frequencies to conserve power and reduce heat generation, thus resolving the contradiction between security performance and computational efficiency.
2Productivity
If encryption tasks are performed on all processor cores, then computational power is increased, but power consumption increases significantly
Solution Approach 1:
The patent applies local quality by assigning different operational characteristics to different processor cores. Specifically, certain cores are designated as encryption-optimized cores with higher operating frequencies and specialized instruction sets, while other cores operate at lower frequencies for general-purpose tasks. This localized differentiation allows the system to achieve high computational power for encryption when needed while minimizing overall power consumption during non-encryption operations.
Solution Approach 2:
The system dynamically adjusts the operating frequency of processor cores based on the current task requirements. When encryption tasks are detected, designated cores are frequency-scaled up to provide maximum computational power. When encryption is not required, these cores are frequency-scaled down to reduce power consumption, thus dynamically balancing computational power and energy usage.
3Loss of time
If processor frequency is increased to reduce encryption time, then encryption speed is improved, but power consumption increases
Solution Approach 1:
The patent segments the processor workload by dedicating specific cores to encryption operations. These encryption-specialized cores can operate at higher frequencies without impacting the power consumption of the entire processor system, as non-encryption cores continue to operate at lower frequencies. This segmentation allows the system to reduce encryption time through targeted frequency increases while minimizing overall power consumption.
Data Source
AI summary
Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes: interface circuitry to receive a first value and a second value; selector circuitry to select a first subset of bits and a second subset of bits from the first value; multiplier circuitry to: multiply the first subset to the second value during a first compute cycle; and multiply the second subset to the second value during a second compute cycle; left shift circuitry to perform a bitwise shift with a product of the first subset and the second value during the second compute cycle; adder circuitry to add a product of the second subset and the second value to a result of the plurality of bitwise shift operations during the second compute cycle; and comparator circuitry to determine the result of the modular multiplication based on a result of the addition during the second compute cycle.