X87 Floating Point Addition Rounding Optimization
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Solution Overview
Problem
The x87 floating point architecture faces performance issues in executing floating point addition instructions due to the variability in rounding determination time, particularly when both addends contribute sticky bits, leading to potential additional clock cycles or prolonged execution times.
Innovation Solution
A microprocessor system that distinguishes between long and short cases of floating point addition instructions based on predetermined conditions related to precision and addend contributions, allowing for selective replay of instructions to optimize execution time by saving intermediate results and re-dispatching for rounding determination when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the x87 FPU performs rounding determination for floating point addition instructions, then the precision of the calculation result is maintained, but the execution time increases particularly when both addends contribute sticky bits
Solution Approach 1:
The patent applies preliminary action by determining whether both addends contribute sticky bits to the rounding determination before actually performing the addition. This early detection allows the system to prepare for potential extended execution time cases in advance, enabling optimization strategies to be applied selectively based on the detected condition.
Solution Approach 2:
The patent implements dynamics by making the execution path variable based on the detected condition. When both addends contribute sticky bits, the system takes a different execution path (extending to N+1 clock cycles) compared to the standard path (N clock cycles). This dynamic adaptation allows the system to maintain precision when needed while minimizing execution time in most cases.
2Measurement precision
If the x87 FPU executes floating point addition instructions in multiple clock cycles to accommodate rounding determination, then the precision is maintained, but the overall performance and productivity decrease
Solution Approach 1:
The patent applies local quality by making the extended precision handling localized to specific cases where both addends contribute sticky bits. The majority of floating point addition instructions continue to execute in the standard N clock cycles, while only the specific subset of instructions requiring extended rounding determination take N+1 cycles. This localized approach minimizes the impact on overall productivity while maintaining precision where required.
Solution Approach 2:
The patent changes the execution time parameter dynamically based on the input characteristics. By detecting whether both addends contribute sticky bits, the system adjusts the number of clock cycles allocated for execution (N or N+1), effectively changing the time parameter to match the computational requirements of each specific instruction.
3Measurement precision
If the x87 FPU uniformly allocates N+1 clock cycles for all floating point addition instructions to ensure precision, then the precision is guaranteed, but the execution time for simple cases increases unnecessarily
Solution Approach 1:
The patent applies partial action by performing the extended rounding determination only when necessary (when both addends contribute sticky bits) rather than for all instructions. The system performs the minimum required action for each case: standard rounding for most instructions and extended rounding only when the specific condition is detected, avoiding unnecessary execution time overhead.
Solution Approach 2:
The patent uses preliminary detection of the sticky bit contribution condition to determine the appropriate execution path before performing the addition. This preliminary action allows the system to avoid allocating N+1 clock cycles for simple cases, reserving the extended execution time only for instructions that actually require it.
Data Source
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AI summary
A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any conditions exist in the addends with respect to their contribution to a rounding determination and relative to the PC field. If none of the conditions exists, the FPU makes the rounding determination based on the smaller addend and the PC field, and selectively rounds the sum based on the rounding determination. If any conditions exist, the FPU saves the sum and rounding information derived from the addends, and signals the instruction dispatcher to re-dispatch the instruction. On re-dispatch, the FPU makes the rounding determination based on the saved rounding information and the PC field, and selectively rounds the sum based on the rounding determination.