XDR DRAM Memory Controller Precharge Scheduling
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Solution Overview
Problem
XDR memory controllers face challenges in efficiently managing command cycles to issue precharge packets due to the lack of auto-precharging support in XDR DRAM architecture, requiring explicit precharge commands and complex scheduling to avoid collisions.
Innovation Solution
The memory controller determines whether concurrent request packets include precharge or non-precharge commands, deferring and adjusting the dynamic offset of precharge commands as necessary to locate an open command cycle, allowing for the merging of precharge commands into a single packet and ensuring proper timing for issuing precharge packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If explicit precharge commands are issued in XDR DRAM architecture without auto-precharging support, then precharge operations can be performed, but command cycle scheduling complexity increases
Solution Approach 1:
The patent detects open command cycles in advance and issues precharge packets during these open cycles before they are needed, rather than waiting until precharge is required. This preliminary action allows the system to prepare precharge operations ahead of time, reducing scheduling complexity during critical execution phases.
Solution Approach 2:
The patent segments the command stream by identifying and separating precharge commands from non-precharge commands. By detecting open command cycles and issuing precharge packets independently during these open cycles, the system divides the scheduling problem into manageable segments, reducing overall scheduling complexity.
2Productivity
If precharge packets are issued during open command cycles, then command cycle efficiency improves, but collision detection and scheduling complexity increases
Solution Approach 1:
The system monitors its own command cycles to detect open cycles where no other packets are currently occupying the bus. By having the memory controller self-detect these open cycles and autonomously issue precharge packets during them, the system improves efficiency without requiring external coordination or complex centralized scheduling.
Solution Approach 2:
The patent dynamically adjusts the timing of precharge packet issuance based on real-time detection of open command cycles. Rather than using fixed scheduling, the system adapts its precharge timing to the actual state of the command bus, improving efficiency while managing complexity through flexible, condition-based scheduling.
3Adaptability or versatility
If dynamic offset adjustment is used to defer precharge commands, then timing flexibility improves, but control logic complexity increases
Solution Approach 1:
The patent changes the timing parameter of precharge commands by adjusting their dynamic offset values. By deferring precharge commands and adjusting their execution timing through offset modification, the system achieves timing flexibility to align precharge operations with detected open command cycles, adapting to varying bus conditions without complex control logic.
Data Source
AI summary
A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determination is made as to whether one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command. If one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command, the request packet having a non-precharge command proceeds. In addition, the precharge command is deferred and its dynamic offset is adjusted accordingly.