XDSL Clock Synchronization via Timestamp Compensation
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Solution Overview
Problem
Current clock synchronization methods in XDSL systems fail to meet the high-precision requirements due to asymmetrical uplink and downlink delays and symbol synchronization offsets, which are exacerbated by complex analog and digital circuit delays in the communication channel.
Innovation Solution
A clock synchronization method that involves reading and correcting time stamps at specific positions of DMT signals, using frequency domain equalizer parameters to determine symbol synchronization offsets, and adjusting the clock of customer premises equipment to synchronize with central office equipment, thereby accounting for circuit delays and ensuring precise synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional time synchronization methods are used in XDSL systems, then the system can operate with existing equipment, but the time synchronization precision cannot meet the microsecond level requirement
Solution Approach 1:
The patent applies preliminary action by pre-calculating and compensating for asymmetrical delays in uplink and downlink channels before performing time synchronization. The system measures the delay difference between uplink and downlink paths in advance, then uses this compensation value to correct timestamp calculations, enabling microsecond-level precision without requiring complex real-time adjustments
Solution Approach 2:
The patent changes the parameter of timestamp correction by introducing compensation values for asymmetrical delays. Instead of using raw timestamps directly, the system modifies the timestamp parameters by adding or subtracting measured delay differences, thereby transforming the synchronization accuracy from insufficient to meeting microsecond-level requirements
2Ease of operation
If time synchronization is performed in the PMD layer, then the synchronization point can be established, but the downlink delay is not equal to the uplink delay due to complex circuits
Solution Approach 1:
The patent explicitly addresses asymmetry by measuring and compensating for the different delays in uplink and downlink channels. Instead of assuming symmetrical delays, the system separately measures the delay in each direction and uses the difference to correct timestamp calculations, thereby resolving the issue of unequal delays caused by complex analog and digital circuits
Solution Approach 2:
The patent implements feedback by measuring the actual delay in the communication channel and using this measured value to adjust the synchronization process. The system continuously monitors the delay difference between uplink and downlink and feeds this information back into the timestamp correction algorithm, ensuring accurate synchronization despite varying channel conditions
3Ease of manufacture
If the channel includes analog circuits and digital signal processing circuits, then the signal can be processed, but the time error after recovery becomes much greater than 1 μs
Solution Approach 1:
The patent extracts and separates the delay contributions from different components (analog circuits, digital signal processing circuits, transmission medium) to individually measure and compensate for each. By taking out the delay measurement from the overall system and analyzing it component-wise, the system can identify and correct the cumulative time errors that would otherwise exceed 1 μs
Data Source
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AI summary
A clock synchronization method, customer premises equipment and a clock synchronization system are provided. The clock synchronization method includes: reading, by customer premises equipment, a first time stamp when receiving a first specific position of a first DMT signal sent by central office equipment; reading a second time stamp when sending a second specific position of a second DMT signal; receiving a third time stamp and a fourth time stamp that are sent by the central office equipment through a data information channel, wherein the third time stamp is read when the central office equipment sends the first specific position of the first DMT signal, and the fourth time stamp is read when the central office equipment receives the second specific position of the second DMT signal; and adjusting a clock of the customer premises equipment according to the first time stamp, the second time stamp, the third time stamp and the fourth time stamp, so that the clock of the customer premises equipment is synchronized with a clock of the central office equipment. The method, the equipment and the system improve precision of clock synchronization and meet a high-precision requirement of an XDSL system on the clock synchronization.