XFET Memory Bit Cell Power Routing With Dual-Polarity Interconnects
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges with capacitive coupling, electro migration, short channel effects, and processing yield, which affect the placement and routing of devices on semiconductor chips, leading to inefficiencies in design and increased time to market.
Innovation Solution
The use of cross field effect transistors (FETs) with an orthogonal orientation, where a top GAA transistor is vertically stacked on a bottom GAA transistor with an isolating oxide layer, allowing for dual polarity local interconnect power connections and reducing on-die area consumption, resistance, and capacitance, while improving carrier mobility and reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor routing techniques are used, then design rules can be followed, but capacitive coupling and electro migration issues arise affecting performance and reliability
Solution Approach 1:
The patent transitions from planar transistor routing to three-dimensional vertically stacked transistor architecture. By stacking transistors vertically with orthogonal channel orientations, the design eliminates capacitive coupling issues inherent in planar layouts while improving power efficiency and signal integrity through reduced parasitic effects and optimized current paths.
2Productivity
If automated place-and-route tools are used, then design cycle is shortened, but performance and power consumption requirements are not met
Solution Approach 1:
The patent changes the fundamental geometric parameters of transistor arrangement by implementing vertical stacking with orthogonal channel orientations. This parameter change enables automated tools to meet performance and power requirements by reducing parasitic capacitance and optimizing current flow paths, while maintaining design automation efficiency.
3Productivity
If more functionality is integrated on smaller die area, then performance increases, but short channel effects and leakage currents increase
Solution Approach 1:
The patent moves from two-dimensional planar transistor layouts to three-dimensional vertically stacked configurations. This dimensional change allows higher functionality density on smaller die areas while reducing short channel effects and leakage currents through orthogonal channel orientations and improved electrostatic control in the vertical dimension.
Data Source
AI summary
A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. One or more of these cells use a dual polarity local interconnect power connection to receive a voltage reference level from a backside bus. For example, a power supply reference voltage level is received by a p-type device from a backside bus where the connection traverses both a p-type local interconnect layer and an n-type local interconnect layer.