xIMD Computing System Lane Forking for Branch Divergence
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Solution Overview
Problem
Single Instruction Multiple Data (SIMD) architectures face performance reduction due to data-dependent branches, where some lanes stall while others continue execution, leading to inefficiency in processing multiple data items simultaneously.
Innovation Solution
The xIMD system automatically creates secondary execution paths by selecting new dominant lanes at data-dependent branches, allowing lanes with different branch states to access secondary instruction memories, thereby migrating from full SIMD to a Multiple Instruction Multiple Data (MIMD) configuration, reducing stalls and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SIMD architecture is used to perform the same operation on multiple data items simultaneously, then processing throughput is improved, but performance degrades when data-dependent branches occur causing lanes to stall
Solution Approach 1:
The patent segments the SIMD lanes into different groups based on their branch execution status. When data-dependent branches occur, lanes are divided into those that take the branch and those that don't, allowing independent execution paths for each segment rather than stalling all lanes. This segmentation enables continuous processing across different lane groups.
Solution Approach 2:
The patent dynamically adjusts the execution mode of different lanes based on runtime branch conditions. Lanes can transition between synchronized SIMD execution and independent MIMD-like execution depending on whether they encounter data-dependent branches. This dynamic adaptation allows the system to maintain high throughput while handling branch divergence.
2Device complexity
If all lanes execute the same instruction stream in SIMD mode, then hardware simplicity is maintained, but execution efficiency decreases when lanes need to follow different execution paths
Solution Approach 1:
The patent makes the instruction memory system multi-functional by enabling it to serve both SIMD and MIMD execution modes. The same instruction memory infrastructure is used for both synchronized lane execution and independent lane execution, avoiding the need for completely separate hardware paths. This universality maintains hardware simplicity while supporting efficient divergent execution.
Solution Approach 2:
The patent introduces an intermediary mechanism that manages instruction delivery to different lane groups. This intermediary layer sits between the instruction memory and the execution units, dynamically routing instructions to appropriate lane groups based on branch status. It mediates between the simple instruction memory structure and the complex runtime execution requirements.
Data Source
AI summary
An integrated circuit may include a mixed instruction multiple data (xIMD) computing system. The xIMD computing system may include a plurality of data processors, each data processor representative of a lane of a single instruction multiple data (SIMD) computing system, wherein the plurality of data processors are configured to use a first dominant lane for instruction execution and to fork a second dominant lane when a data dependency instruction that does not share a taken/not-taken state with the first dominant lane is encountered during execution of a program by the xIMD computing system.