XMSS Verification Hardware for Low-Latency Secure Boot

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Solution Overview

Problem

Existing public-key digital signature algorithms such as RSA and ECDSA are vulnerable to brute-force attacks from quantum computers, necessitating the development of secure hash-based signature schemes like XMSS and LMS to protect against quantum computing threats.

Innovation Solution

Implementing accelerators for post-quantum cryptography secure hash-based signature algorithms, specifically XMSS and LMS, using hardware accelerators to reduce the computational latency in signature verification processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If hardware accelerators are used for post-quantum cryptography signature verification, then signature verification speed is improved, but device complexity increases

Engineering Contradiction:

Improvesignature verification speedVSAvoiddevice complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The signature verification process is divided into distinct modular components: hash chain computation units, Merkle tree verification units, and authentication path validation units. Each module handles a specific aspect of the verification process, enabling parallel execution and improving overall speed while keeping individual module complexity manageable.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces dedicated hardware accelerator circuits as intermediary components between the processor and the cryptographic operations. These accelerators offload complex post-quantum cryptographic computations from the general-purpose processor, providing specialized high-speed processing without requiring the entire system to become complex.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If quantum-resistant algorithms are implemented, then security against quantum attacks is improved, but computational latency increases

Engineering Contradiction:

Improvesecurity against quantum attacksVSAvoidcomputational latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary computation of hash chains and Merkle tree structures during key generation and stores them in hardware registers. This pre-computation eliminates the need for repeated expensive calculations during signature verification, maintaining quantum-resistant security while significantly reducing operational latency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The hardware accelerator maintains continuous operation through pipelined execution of cryptographic operations. Multiple verification steps are overlapped in time, with data flowing continuously through the computation pipeline, ensuring that security operations complete faster without compromising the integrity of quantum-resistant algorithms.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentEP3758284B1Low latency post-quantum signature verification for fast secure-boot

Publication Date: 2025.09.03 INTEL CORP

Figure 1A~1B
Figure 2A
Figure 2B

AI summary

In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.