XNOR Full Adder Cell With Reduced Transistor Count
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Solution Overview
Problem
Conventional full adder circuits consume significant power and occupy large areas due to the high number of transistors required, which hinders the development of more powerful, compact, and efficient digital logic circuits.
Innovation Solution
The design incorporates a two-input exclusive NOR gate implemented as a NAND gate combined with an OR-AND-INVERTER cell, sharing signals between logic stages, and utilizing a novel pass gate structure to reduce the number of transistors, resulting in a full adder circuit with improved power characteristics and performance for 4:2 and higher-order compressors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional full adder circuits are implemented using multiple transistors arranged as inverters, pass gates, AND gates, OR gates, and XOR gates, then the circuit achieves complete adder functionality, but the transistor count increases significantly, occupying large chip area and consuming more power
Solution Approach 1:
The patent combines multiple logic gates into integrated structures. Specifically, it uses a 5:2 compressor cell that merges full adder functionality with carry lookahead logic, and a 6:2 compressor cell that further integrates additional compression functions. These merged structures reduce the total transistor count while maintaining complete adder functionality across multiple operands.
Solution Approach 2:
The compressor cells designed in the patent serve multiple functions simultaneously. The 5:2 compressor cell can function as both a full adder and a carry lookahead unit, while the 6:2 compressor cell provides enhanced compression capabilities. This multi-functionality eliminates the need for separate dedicated circuits for each operation, reducing overall chip area.
2Reliability
If conventional full adder circuits use thousands of transistors for hundreds of adders, then complete logical functionality is achieved, but power consumption increases significantly
Solution Approach 1:
By merging full adder logic with carry lookahead and compression functions into unified compressor cells, the patent reduces the total number of transistor switches. Fewer transistors mean fewer switching events and lower dynamic power consumption while maintaining complete adder functionality for multiple operands.
Solution Approach 2:
The patent extracts and eliminates redundant logic stages from conventional full adder implementations. By using compressor cells that directly compute multiple sum and carry outputs in fewer stages, unnecessary intermediate switching operations are removed, reducing power consumption.
3Measurement precision
If conventional full adder circuits implement complete logic functions with multiple gates, then accurate addition is achieved, but the number of logic stages increases, slowing down operational speed
Solution Approach 1:
The carry lookahead logic embedded in the compressor cells performs preliminary carry computation in parallel with sum generation. Instead of waiting for sequential carry propagation through multiple stages, the lookahead logic predicts and prepares carry values in advance, significantly reducing the critical path delay while maintaining accurate addition results.
Solution Approach 2:
The patent segments the addition operation into independent compressor cells that process multiple operands simultaneously. Each 5:2 or 6:2 compressor cell handles a specific group of inputs and generates intermediate sums and carries that are then combined in subsequent stages, allowing parallel processing that accelerates overall operation speed.
Data Source
AI summary
An adder circuit that includes an operand input and a second operand input to an XNOR cell. The XNOR cell is configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell transforms the output of the XNOR cell into a carry out signal.