XNOR Multiplier-Accumulator for Accurate Signed MAC Summation
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Solution Overview
Problem
Current multiplier-accumulator designs for neural networks face inefficiencies in performing MAC operations due to limitations in handling negative numbers and fractional parts, leading to errors in summation processes.
Innovation Solution
The design incorporates exclusive negative OR (XNOR) gates and encoders that convert most significant bits (MSBs) from 2's complement to a new number system, allowing for accurate multiplication and accumulation while compensating for errors through correction values, thereby enhancing operation speed and reducing area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multiplier-accumulator designs are used for neural networks, then basic MAC operations can be performed, but errors occur in handling negative numbers and fractional parts during summation processes
Solution Approach 1:
The patent changes the number system parameter from conventional binary to a new number system where the most significant bit represents a negative weight. This parameter change enables accurate representation and summation of negative numbers and fractional parts without requiring complex error correction logic, thereby improving reliability while maintaining reasonable hardware complexity
Solution Approach 2:
The patent replaces complex error detection and correction mechanisms with a fundamentally different numerical representation system. By substituting the conventional approach of adding error correction hardware with a new number system that inherently prevents errors, the design achieves higher reliability without proportionally increasing hardware complexity
2Productivity
If conventional MAC operation designs are used, then standard processing can be performed, but processing speed is limited due to inefficiencies in handling negative numbers and fractional parts
Solution Approach 1:
By changing the numerical representation parameter to a new number system with negative weight MSB, the patent enables more efficient MAC operations. This parameter change allows direct summation without complex error correction steps, improving both processing speed and accuracy simultaneously
3Reliability
If conventional approaches are used to handle negative numbers and fractional parts, then basic functionality is maintained, but area requirements increase due to additional error correction hardware
Solution Approach 1:
The patent changes the fundamental parameter of numerical representation to eliminate the need for separate error correction hardware. The new number system's inherent structure allows accurate handling of negative numbers and fractional parts using the same basic MAC circuitry, thereby improving reliability without increasing hardware area
Data Source
AI summary
A multiplier-accumulator includes: a plurality of exclusive negative OR (XNOR) gates provided along one or more input lines and configured to receive signals corresponding to an input bit sequence and a weight bit sequence corresponding to each of the one or more input lines and to output partial product results between the input bit sequence and the weight bit sequence; an encoder configured to apply, to the plurality of XNOR gates, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is converted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of the input bit sequence and the weight bit sequence; and an outputter configured to generate an output in which a correction value is applied to operation results in which the partial product results output from the plurality of XNOR gates are summed.